[PATCH v2 0/3] Support additional AMD EILVT registers

[Naveen N Rao (AMD)]

This is v2 of the series posted at:
http://lore.kernel.org/r/cover.1775019269.git.naveen@xxxxxxxxxx

Changes since v1:
- Drop the first two patches that were merged
- Call init_eilvt() from apic_bsp_setup(), rather than 
  setup_local_APIC() so as not to call an __init function from a 
  non-init function. (Kernel 0-day bot)
- Initialize eilvt count to APIC_EILVT_NR_AMD_10H and allocate 
  eilvt_offsets array only on AMD processors.
 
Manali,
I am retaining your Tested-by: tag since the changes are minimal, but 
please reply here if you have concerns with the changes.

--
Future AMD processors will be increasing the number of APIC EILVT 
registers (*). This series adds support for the same along with some 
related cleanups.

(*) https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)


- Naveen


Naveen N Rao (AMD) (3):
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  2 +-
 arch/x86/events/amd/ibs.c      |  4 ++--
 arch/x86/kernel/apic/apic.c    | 19 +++++++++++++++++--
 4 files changed, 22 insertions(+), 5 deletions(-)


base-commit: 70e7aca9f7ff4d1bee94c5b04973c3dbca1dba00
-- 
2.54.0