[PATCH 1/2] irqchip/irq-realtek-rtl: Add/simplify register helpers

[Markus Stockhausen]

The Realtek IRQ controller has two important registers that
are used by the driver in several places

- GIMR: global interrupt mask register
- IRR: Interrupt routing registers

The usage of these registers is very inconsistent. GIMR is
addressed directly while IRR has a helper that needs an
macro as an input. Harmonize this by providing consistent
helpers that improve code readability.

Signed-off-by: Markus Stockhausen <markus.stockhausen@xxxxxx>
---
 drivers/irqchip/irq-realtek-rtl.c | 48 +++++++++++++++++++------------
 1 file changed, 29 insertions(+), 19 deletions(-)

diff --git a/drivers/irqchip/irq-realtek-rtl.c b/drivers/irqchip/irq-realtek-rtl.c
index 942c1f8c363d..7fb8dd4c5670 100644
--- a/drivers/irqchip/irq-realtek-rtl.c
+++ b/drivers/irqchip/irq-realtek-rtl.c
@@ -37,10 +37,29 @@ static void __iomem *realtek_ictl_base;
 #define IRR_OFFSET(idx)		(4 * (3 - (idx * 4) / 32))
 #define IRR_SHIFT(idx)		((idx * 4) % 32)
 
-static void write_irr(void __iomem *irr0, int idx, u32 value)
+static inline void enable_gimr(int hw_irq)
 {
-	unsigned int offset = IRR_OFFSET(idx);
-	unsigned int shift = IRR_SHIFT(idx);
+	u32 gimr;
+
+	gimr = readl(REG(RTL_ICTL_GIMR));
+	gimr |= BIT(hw_irq);
+	writel(gimr, REG(RTL_ICTL_GIMR));
+}
+
+static inline void disable_gimr(int hwirq)
+{
+	u32 gimr;
+
+	gimr = readl(REG(RTL_ICTL_GIMR));
+	gimr &= ~BIT(hwirq);
+	writel(gimr, REG(RTL_ICTL_GIMR));
+}
+
+static void write_irr(int hw_irq, u32 value)
+{
+	void __iomem *irr0 = REG(RTL_ICTL_IRR0);
+	unsigned int offset = IRR_OFFSET(hw_irq);
+	unsigned int shift = IRR_SHIFT(hw_irq);
 	u32 irr;
 
 	irr = readl(irr0 + offset) & ~(0xf << shift);
@@ -51,28 +70,18 @@ static void write_irr(void __iomem *irr0, int idx, u32 value)
 static void realtek_ictl_unmask_irq(struct irq_data *i)
 {
 	unsigned long flags;
-	u32 value;
 
 	raw_spin_lock_irqsave(&irq_lock, flags);
-
-	value = readl(REG(RTL_ICTL_GIMR));
-	value |= BIT(i->hwirq);
-	writel(value, REG(RTL_ICTL_GIMR));
-
+	enable_gimr(i->hwirq);
 	raw_spin_unlock_irqrestore(&irq_lock, flags);
 }
 
 static void realtek_ictl_mask_irq(struct irq_data *i)
 {
 	unsigned long flags;
-	u32 value;
 
 	raw_spin_lock_irqsave(&irq_lock, flags);
-
-	value = readl(REG(RTL_ICTL_GIMR));
-	value &= ~BIT(i->hwirq);
-	writel(value, REG(RTL_ICTL_GIMR));
-
+	disable_gimr(i->hwirq);
 	raw_spin_unlock_irqrestore(&irq_lock, flags);
 }
 
@@ -89,7 +98,7 @@ static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 	irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);
 
 	raw_spin_lock_irqsave(&irq_lock, flags);
-	write_irr(REG(RTL_ICTL_IRR0), hw, 1);
+	write_irr(hw, 1);
 	raw_spin_unlock_irqrestore(&irq_lock, flags);
 
 	return 0;
@@ -135,9 +144,10 @@ static int __init realtek_rtl_of_init(struct device_node *node, struct device_no
 		return -ENXIO;
 
 	/* Disable all cascaded interrupts and clear routing */
-	writel(0, REG(RTL_ICTL_GIMR));
-	for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++)
-		write_irr(REG(RTL_ICTL_IRR0), soc_irq, 0);
+	for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) {
+		disable_gimr(soc_irq);
+		write_irr(soc_irq, 0);
+	}
 
 	if (WARN_ON(!of_irq_count(node))) {
 		/*
-- 
2.54.0