Re: [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration

[Jian Hu]

Hi Brain,


Thanks for your review.

On 5/11/2026 11:21 PM, Brian Masney wrote:
> [ EXTERNAL EMAIL ]
>
> On Mon, May 11, 2026 at 08:47:28PM +0800, Jian Hu via B4 Relay wrote:
> > From: Jian Hu <jian.hu@xxxxxxxxxxx>
> >
> > In the A9 design, the PLL reset signal is configured as active-low.
> >
> > Add the flag 'CLK_MESON_PLL_RST_N' to indicate that the PLL reset signal
> > is active-low.
> This flag isn't in the patch. I assume that you mean
> CLK_MESON_PLL_RST_ACTIVE_LOW?
>
> Brian


Yes,  You are right, the flag should indeed be CLK_MESON_PLL_RST_ACTIVE_LOW.

I will fix the description in the next version.

Thank you for pointing it out.


[......]


Best regards,

Jian