Re: [PATCH v5 10/17] dmaengine: sh: rz-dmac: Refactor pause/resume code

[Claudiu Beznea]

Hi, Frank,

On 5/13/26 00:43, Frank Li wrote:
> On Tue, May 12, 2026 at 03:12:11PM +0300, Claudiu Beznea wrote:
> > Subsequent patches will add suspend/resume and cyclic DMA support to the
> > rz-dmac driver. This support needs to work on SoCs where power to most
> > components (including DMA) is turned off during system suspend. For this,
> > some channels (for example cyclic ones) may need to be paused and resumed
> > manually by the DMA driver during system suspend/resume.
> >
> > Refactor the pause/resume support so the same code can be reused in the
> > system suspend/resume path.
> >
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> > ---
> >
> > Changes in v5:
> > - none
> >
> > Changes in v4:
> > - reset channel->status in rz_dmac_free_chan_resources() and
> >    rz_dmac_terminate_all()
> >
> > Changes in v3:
> > - none, this patch new new
> >
> >   drivers/dma/sh/rz-dmac.c | 73 ++++++++++++++++++++++++++++++++++------
> >   1 file changed, 62 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> > index 53ee9fe65261..2bf796dcc5f6 100644
> > --- a/drivers/dma/sh/rz-dmac.c
> > +++ b/drivers/dma/sh/rz-dmac.c
> > @@ -18,6 +18,7 @@
> >   #include <linux/irqchip/irq-renesas-rzv2h.h>
> >   #include <linux/irqchip/irq-renesas-rzt2h.h>
> >   #include <linux/list.h>
> > +#include <linux/lockdep.h>
> >   #include <linux/module.h>
> >   #include <linux/of.h>
> >   #include <linux/of_dma.h>
> > @@ -63,6 +64,14 @@ struct rz_dmac_desc {
> >
> >   #define to_rz_dmac_desc(d)	container_of(d, struct rz_dmac_desc, vd)
> >
> > +/**
> > + * enum rz_dmac_chan_status: RZ DMAC channel status
> > + * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callbacks
> > + */
> > +enum rz_dmac_chan_status {
> > +	RZ_DMAC_CHAN_STATUS_PAUSED,
> > +};
> > +
>
> Not sure why use BIT() for each status? suppose only one certain state

Later (in the next patches), a channel could be paused (or paused internally) 
and cyclic at the same time. This way we can keep a single member in struct 
rz_dmac_chan for all these and execute a single instruction when clearing the 
status bit (e.g. in rz_dmac_free_chan_resources(), rz_dmac_terminate_all()).

I consider this more compact than having individual state variables for all these.

--
Thank you,
Claudiu