Re: [PATCH v5 1/4] dmaengine: fsl-edma: use devm_clk_get_optional_enabled() for channel clock
From: Frank Li
Date: Wed May 13 2026 - 10:57:32 EST
On Wed, May 13, 2026 at 07:23:47PM +0800, Joy Zou wrote:
> The channel clock is optional and not present on all platforms. Replace
> devm_clk_get_enabled() with devm_clk_get_optional_enabled() and remove
> FSL_EDMA_DRV_HAS_CHCLK flag to simplify clock handling.
>
> Prepare to add channel runtime pm support.
>
> Signed-off-by: Joy Zou <joy.zou@xxxxxxx>
> ---
Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> drivers/dma/fsl-edma-common.c | 4 +---
> drivers/dma/fsl-edma-common.h | 1 -
> drivers/dma/fsl-edma-main.c | 18 ++++++------------
> 3 files changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index bb7531c456dfa0a8812883a2cf3e9e2e23b0f55e..e1ca25ff228dbe392bb800f6ecac5a85ca326bf1 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -844,9 +844,7 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
> struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
> int ret = 0;
>
> - if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
> - clk_prepare_enable(fsl_chan->clk);
> -
> + clk_prepare_enable(fsl_chan->clk);
> fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
> fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ?
> sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd),
> diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
> index 205a96489094805aa728b72a51ae101cd88fa003..f4354b586746d64faf375cc9ce04e15a7b6d86ab 100644
> --- a/drivers/dma/fsl-edma-common.h
> +++ b/drivers/dma/fsl-edma-common.h
> @@ -210,7 +210,6 @@ struct fsl_edma_desc {
> #define FSL_EDMA_DRV_WRAP_IO BIT(3)
> #define FSL_EDMA_DRV_EDMA64 BIT(4)
> #define FSL_EDMA_DRV_HAS_PD BIT(5)
> -#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
> #define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
> #define FSL_EDMA_DRV_MEM_REMOTE BIT(8)
> /* control and status register is in tcd address space, edma3 reg layout */
> diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
> index 36155ab1602a9b264df73dbde3ec2b3aa6cc27c0..87f575d6ccafff455d47f8c794a503abf97e2af1 100644
> --- a/drivers/dma/fsl-edma-main.c
> +++ b/drivers/dma/fsl-edma-main.c
> @@ -567,8 +567,7 @@ static struct fsl_edma_drvdata imx8qm_data = {
> };
>
> static struct fsl_edma_drvdata imx8ulp_data = {
> - .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK |
> - FSL_EDMA_DRV_EDMA3,
> + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
> .chreg_space_sz = 0x10000,
> .chreg_off = 0x10000,
> .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
> @@ -808,22 +807,17 @@ static int fsl_edma_probe(struct platform_device *pdev)
> fsl_chan->tcd = fsl_edma->membase
> + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
> fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
> + snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
> + fsl_chan->clk = devm_clk_get_optional_enabled(&pdev->dev, (const char *)clk_name);
>
> - if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
> - snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
> - fsl_chan->clk = devm_clk_get_enabled(&pdev->dev,
> - (const char *)clk_name);
> -
> - if (IS_ERR(fsl_chan->clk))
> - return PTR_ERR(fsl_chan->clk);
> - }
> + if (IS_ERR(fsl_chan->clk))
> + return PTR_ERR(fsl_chan->clk);
> fsl_chan->pdev = pdev;
> vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
>
> edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr);
> fsl_edma_chan_mux(fsl_chan, 0, false);
> - if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK)
> - clk_disable_unprepare(fsl_chan->clk);
> + clk_disable_unprepare(fsl_chan->clk);
> }
>
> ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
>
> --
> 2.37.1
>