ad7768-1: GPIO reset path delays do not match the datasheet

From: Stepan Ionichev

Date: Wed May 13 2026 - 11:01:28 EST


Hi all,

Reading drivers/iio/adc/ad7768-1.c I noticed the GPIO reset path
uses two bare fsleep() calls that seem to disagree with the AD7768-1
datasheet (Rev. B). I do not have AD7768-1 hardware to test this,
so I am reporting it rather than sending a patch -- maybe someone
with a board can verify and fix.

Code (drivers/iio/adc/ad7768-1.c, around lines 1249-1252):

if (st->gpio_reset) {
fsleep(10);
gpiod_set_value_cansleep(st->gpio_reset, 0);
fsleep(200);
}

Compared with the datasheet (AD7768-1 Rev. B, page 6, Table 1
"Specifications", ADC RESET section):

Reset Low Pulse Width minimum 100 us
ADC Start-Up Time After Reset 17 ms
(Reset rising edge to first DRDY,
PIN mode, decimate by 8)

So the in-tree code:
- holds the RESET pin low for ~10 us, where the datasheet
requires a minimum of 100 us;
- waits ~200 us after deasserting RESET before issuing SPI
traffic / set_mode, where the datasheet specifies 17 ms from
the reset rising edge to the first DRDY.

The neighbouring SPI-reset branch already cites the datasheet
(page 70), which is why this jumped out.

If anyone with an AD7768-1 board can confirm whether the chip
actually needs the datasheet-spec timing (or whether something
else makes the shorter waits fine in practice), this looks worth
a follow-up patch -- something like:

if (st->gpio_reset) {
/* RESET low pulse width: datasheet Rev. B, page 6,
* Table 1, min 100 us. */
fsleep(100);
gpiod_set_value_cansleep(st->gpio_reset, 0);
/* ADC start-up time after reset: datasheet Rev. B,
* page 6, Table 1, 17 ms (reset rising edge to first
* DRDY, PIN mode, decimate by 8). */
msleep(17);
}

I am happy to send the patch myself if someone with hardware
confirms it does not regress -- I would rather not submit an
untested timing change blind.

Stepan