Re: [PATCH 5/5] arm_mpam: detect and enable MPAM-Fb PCC support

[Andre Przywara]

Hi Ben,

On 5/8/26 12:48, Ben Horgan wrote:
> Hi Andre,
>
> On 4/29/26 15:13, Andre Przywara wrote:
> > The Arm MPAM-Fb specification [1] describes a protocol to access MSC
> > registers through a firmware interface. This requires a shared memory
> > region to hold the message, and a mailbox to trigger the access.
> > For ACPI this is wrapped as a PCC channel, described using existing
> > ACPI abstractions.
> >
> > Add code to parse those PCC table descriptions associated with an MSC,
> > and store the parsed information in the MSC struct.
> > This will be used by the MPAM-Fb access wrapper code.
> >
> > [1] https://developer.arm.com/documentation/den0144/latest
> >
> > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> > ---
> >   drivers/acpi/arm64/mpam.c      |  2 ++
> >   drivers/resctrl/mpam_devices.c | 46 +++++++++++++++++++++++++++++++---
> >   2 files changed, 45 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/acpi/arm64/mpam.c b/drivers/acpi/arm64/mpam.c
> > index 99c2bdbb3314..edb4d10e8dc3 100644
> > --- a/drivers/acpi/arm64/mpam.c
> > +++ b/drivers/acpi/arm64/mpam.c
> > @@ -341,6 +341,8 @@ static struct platform_device * __init acpi_mpam_parse_msc(struct acpi_mpam_msc_
> >   	} else if (iface == MPAM_IFACE_PCC) {
> >   		props[next_prop++] = PROPERTY_ENTRY_U32("pcc-channel",
> >   							tbl_msc->base_address);
> > +		props[next_prop++] = PROPERTY_ENTRY_U32("msc-id",
> > +							tbl_msc->identifier);
> >   	}
> >   
> >   	acpi_mpam_parse_irqs(pdev, tbl_msc, res, &next_res);
> > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
> > index 62aa04cb6905..6f0d0959d3a4 100644
> > --- a/drivers/resctrl/mpam_devices.c
> > +++ b/drivers/resctrl/mpam_devices.c
> > @@ -19,6 +19,7 @@
> >   #include <linux/irqdesc.h>
> >   #include <linux/list.h>
> >   #include <linux/lockdep.h>
> > +#include <linux/mailbox_client.h>
> >   #include <linux/mutex.h>
> >   #include <linux/platform_device.h>
> >   #include <linux/printk.h>
> > @@ -27,6 +28,9 @@
> >   #include <linux/types.h>
> >   #include <linux/workqueue.h>
> >   
> > +#include <acpi/pcc.h>
> > +#include <acpi/acpi_io.h>
> > +
> >   #include "mpam_internal.h"
> >   #include "mpam_fb.h"
> >   
> > @@ -1042,7 +1046,8 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
> >   
> >   	mpam_mon_sel_lock_held(msc);
> >   
> > -	WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
> > +	if (msc->iface == MPAM_IFACE_MMIO)
> > +		WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
>
> This should be in a different patch.

Which one, preferably? A separate one? Or patch 3/5, which adds the PCC 
access code?
This one here is the patch that enables non-MMIO accesses, so I figured 
that's the place we should relax this check.

> >   	WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
> >   
> >   	mbwu_l_high2 = __mpam_read_reg(msc, MSMON_MBWU_L + 4);
> > @@ -2042,10 +2047,15 @@ static void mpam_msc_drv_remove(struct platform_device *pdev)
> >   	mpam_free_garbage();
> >   }
> >   
> > +static void mpam_pcc_rx_callback(struct mbox_client *cl, void *msg)
> > +{
> > +	/* TODO: wake up tasks blocked on this MSC's PCC channel */
> > +}
> > +
> >   static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev)
> >   {
> >   	int err;
> > -	u32 tmp;
> > +	u32 pcc_subspace_id;
> >   	struct mpam_msc *msc;
> >   	struct resource *msc_res;
> >   	struct device *dev = &pdev->dev;
> > @@ -2090,7 +2100,8 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev)
> >   	if (err)
> >   		return ERR_PTR(err);
> >   
> > -	if (device_property_read_u32(&pdev->dev, "pcc-channel", &tmp))
> > +	if (device_property_read_u32(&pdev->dev, "pcc-channel",
> > +				     &pcc_subspace_id))
> >   		msc->iface = MPAM_IFACE_MMIO;
> >   	else
> >   		msc->iface = MPAM_IFACE_PCC;
> > @@ -2106,6 +2117,35 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev)
> >   		}
> >   		msc->mapped_hwpage_sz = msc_res->end - msc_res->start;
> >   		msc->mapped_hwpage = io;
> > +	} else if (msc->iface == MPAM_IFACE_PCC) {
> > +		u32 msc_id;
> > +
> > +		msc->pcc_cl.dev = &pdev->dev;
> > +		msc->pcc_cl.rx_callback = mpam_pcc_rx_callback;
> > +		msc->pcc_cl.tx_block = false;
>
> How do we make sure that, for instance, a MON_SEL write has completed before we start reading
> the associated counters? Is there an ordering guarantee?

What is your concern here, exactly? To group all the accesses selected 
by one MON_SEL write, we have the mon_sel lock (now mutex) already. And 
on the mbox side I think we are safe because the PCC channel is 
exclusive, we have the per-channel mutex (pcc_chan_lock, in patch 3/5), 
and we wait for confirmation from the other end, even for writes. So as 
long as the MON_SEL write appears in program order before the counter 
read, all should be good, no? Am I missing something?

Cheers,
Andre

> Thanks,
>
> Ben
>
> > +		msc->pcc_cl.tx_tout = 1000; /* 1s */
> > +		msc->pcc_cl.knows_txdone = false;
> > +
> > +		if (device_property_read_u32(&pdev->dev, "msc-id", &msc_id)) {
> > +			pr_err("missing MPAM-Fb MSC identifier\n");
> > +			return ERR_PTR(-EINVAL);
> > +		}
> > +		msc->mpam_fb_msc_id = msc_id;
> > +
> > +		msc->pcc_chan = pcc_mbox_request_channel(&msc->pcc_cl,
> > +							 pcc_subspace_id);
> > +		if (IS_ERR(msc->pcc_chan)) {
> > +			pr_err("Failed to request MSC PCC channel\n");
> > +			return (void *)msc->pcc_chan;
> > +		}
> > +
> > +		if (msc->pcc_chan->shmem_size < MPAM_FB_MAX_MSG_SIZE) {
> > +			pr_err("MPAM-Fb PCC channel size too small.\n");
> > +			pcc_mbox_free_channel(msc->pcc_chan);
> > +			return ERR_PTR(-ENOMEM);
> > +		}
> > +
> > +		mutex_init(&msc->pcc_chan_lock);
> >   	} else {
> >   		return ERR_PTR(-EINVAL);
> >   	}