Re: [PATCH] Documentation: intel_pstate: Fix description of asymmetric packing with SMT

[Rafael J. Wysocki]

On Fri, Apr 24, 2026 at 11:42 PM Ricardo Neri
<ricardo.neri-calderon@xxxxxxxxxxxxxxx> wrote:
>
> The patchset [1], of which commits 046a5a95c3b0 ("x86/sched/itmt: Give all
> SMT siblings of a core the same priority") and 995998ebdebd ("x86/sched:
> Remove SD_ASYM_PACKING from the SMT domain flags") are part, overhauled how
> the scheduler handles asym_packing on x86 hybrid processors with SMT. It
> removed SD_ASYM_PACKING from the x86 SMT scheduling domain and made all SMT
> siblings of a core share the same priority. As a result, asym_packing
> operates only across physical cores, spreading tasks among them and only
> using idle SMT siblings once all physical cores are busy.
>
> Fix the documentation to reflect this behavior.
>
> Fixes: f20af84c29b2 ("cpufreq: intel_pstate: Document hybrid processor support")
> Link: https://lore.kernel.org/r/20230406203148.19182-1-ricardo.neri-calderon@xxxxxxxxxxxxxxx [1]
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@xxxxxxxxxxxxxxx>
> ---
>  Documentation/admin-guide/pm/intel_pstate.rst | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/admin-guide/pm/intel_pstate.rst b/Documentation/admin-guide/pm/intel_pstate.rst
> index fde967b0c2e0..25fe5d88fea6 100644
> --- a/Documentation/admin-guide/pm/intel_pstate.rst
> +++ b/Documentation/admin-guide/pm/intel_pstate.rst
> @@ -355,11 +355,12 @@ HyperThreading (HT) in the context of Intel processors, is enabled on at least
>  one core, ``intel_pstate`` assigns performance-based priorities to CPUs.  Namely,
>  the priority of a given CPU reflects its highest HWP performance level which
>  causes the CPU scheduler to generally prefer more performant CPUs, so the less
> -performant CPUs are used when the other ones are fully loaded.  However, SMT
> -siblings (that is, logical CPUs sharing one physical core) are treated in a
> -special way such that if one of them is in use, the effective priority of the
> -other ones is lowered below the priorities of the CPUs located in the other
> -physical cores.
> +performant CPUs are used when the other ones are fully loaded.  SMT siblings
> +(that is, logical CPUs sharing one physical core) are given the same priority.
> +The scheduler can pull tasks from lower-priority cores and place them on any
> +sibling.  Since the scheduler spreads tasks among physical cores, tasks will be
> +placed on the SMT siblings of physical cores only after all physical cores are
> +busy.
>
>  This approach maximizes performance in the majority of cases, but unfortunately
>  it also leads to excessive energy usage in some important scenarios, like video
>
> ---

Applied (with some edits in the changelog) as 7.1-rc material, thanks!