Re: [PATCH v2 0/2] A proposal to add a gpio-locked fixed clock driver.

[Krzysztof Kozlowski]

On Sun, May 10, 2026 at 06:06:21PM +0000, Vyacheslav Yurkov wrote:
> A gpio-locked fixed clock aggregates one or more input clocks and/or one
> or more GPIOs. It's similar to a gated-fixed-clock, but GPIO direction is
> inverted. Consumers can use the output clock to wait until all input
> clocks are locked and only then initialize / access dependent peripherals.
> 
> The usage example for such a driver is when peripherals depend on PLLs in
> a FPGA, which can't be directly accessed by the CPU, but need a GPIO pin
> to check whether clock is actually usable. E.g. some of the IPs might not
> have a proper split between registers and IP core, which means that if an
> external clock and/or PLL lock is missing and one tries to access the 
> registers, the response never comes, thus the CPU stalls.
> 
> Signed-off-by: Vyacheslav Yurkov <uvv.mail@xxxxxxxxx>
> Signed-off-by: Vyacheslav Yurkov <V.Yurkov.EXT@xxxxxxxxxx>
> ---
> Changes in v2:
> - Renamed to clk-gpio-locked to express intent.
> - Provide enable() / is_enabled() operations so the clock behaves as
>   expected
> - Fixed DTS errors / warnings
> - Link to v1: https://lore.kernel.org/r/20260318-feature-clock-guard-v1-0-6137cb4084b7@xxxxxxxxxx
> 
> ---

Please format your submission properly - read DT bindings submitting
patches, add proper blank lines in the schema, use generic node names so
that we can avoid commenting trivialities.

Best regards,
Krzysztof