[PATCH 00/11] perf/x86/intel: Fix inaccurate hard-coded event configurations

[Dapeng Mi]

Currently, the Intel perf code defines several hard-coded event
configurations for each platform. These configurations include event
constraints, extra MSR settings, and predefined extra MSR values for
certain cache events.

For example, the following five hard-coded event configurations are
defined for Sapphire Rapids:
- intel_glc_event_constraints[]: Non-PEBS event constraints.
- intel_glc_pebs_event_constraints[]: PEBS event constraints.
- intel_glc_extra_regs[]: Event-to-extra MSR mapping for events requiring
  extra MSR access.
- glc_hw_cache_event_ids[]: Cache event IDs.
- glc_hw_cache_extra_regs[]: Extra MSR values for L3 and node events,
  mainly for OCR/OMR events.

However, these hard-coded configurations can become outdated or incorrect
as perfmon events are continuously updated
(see: https://github.com/intel/perfmon). This can result in events being
scheduled on incorrect hardware counters, leading to inaccurate counts,
especially for legacy cache events such as llc-load-misses and
llc-store-misses. While these legacy events are less commonly used since
the introduction of JSON-based cache events, it is still important to keep
them accurate.

This patchset addresses all identified mismatches on mainstream platforms,
including server platforms (ICX, SPR, EMR, GNR, DMR, SRF, and CWF) and
client platforms (ADL, MTL, LNL, ARL, PTL, and NVL).

Note: Due to issues in the 7.1-rc2 release that cause boot-up hangs on
Intel hybrid platforms, this patchset was developed and tested against the
7.0 release.

Testing:
All tests below were run on the platforms mentioned above, with no issues
found:
1. Perf counting test:
   $perf test 114
2. Perf sampling test:
   $perf test 148
3. Legacy LLC cache events counting test:
   $perf stat -e llc-loads,llc-load-misses,llc-stores,llc-store-misses -a

Dapeng Mi (11):
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    ICX
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    SPR
  perf/x86/intel: Update event constraints for DMR
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    ADL
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    MTL
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    LNL
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    ARL
  perf/x86/intel: Update event constraints for PTL
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    NVL
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    SRF
  perf/x86/intel: Update event constraints and cache_extra_regs[] for
    CWF

 arch/x86/events/intel/core.c | 476 +++++++++++++++++++++++++++++------
 arch/x86/events/intel/ds.c   |  23 +-
 arch/x86/events/perf_event.h |   4 +-
 3 files changed, 421 insertions(+), 82 deletions(-)


base-commit: 028ef9c96e96197026887c0f092424679298aae8
-- 
2.34.1