Re: [PATCH v3 01/10] ASoC: dt-bindings: renesas,fsi: add support multiple clocks

[Bui Duc Phuc]

My apologies for the inaccurate description earlier.

> I see your point. What I intended to describe was the internal divider
> configuration for Port A/B within the FSIDIV block, not separate clock
> representations in CCF.
> I will rephrase this as:
> DIVA/DIVB divider settings used for audio clock generation.

In terms of hardware, FSIDIV is an independent block from the FSI IP.
It is declared in the DTS as a separate clock provider as follows:

+    fsidiva_clk: fsidiva_clk@fe1f8000 {
+        compatible = "renesas,r8a7740-fsidiv-clock";
+        reg = <0xfe1f8000 4>;
+        clocks = <&fsia_clk>;
+        #clock-cells = <0>;
+        clock-output-names = "diva";
+    };
+
+    fsidivb_clk: fsidivb_clk@fe1f8008 {
+        compatible = "renesas,r8a7740-fsidiv-clock";
+        reg = <0xfe1f8008 4>;
+        clocks = <&fsib_clk>;
+        #clock-cells = <0>;
+        clock-output-names = "divb";
+    };