Re: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers

[Naveen N Rao]

On Fri, May 15, 2026 at 06:30:07AM -0700, Christian Ludloff wrote:
> On Fri, May 15, 2026 at 4:48 AM Christian Ludloff <ludloff@xxxxxxxxx> wrote:
> >
> > > + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
> > > + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
> >
> > BKDG #21656, #21922, and #24141 for K7 were not published.
> > If you find them internally at AMD, consider publishing them.  :)
> > That way they could be archived, and referenced from then on.
> 
> minor extra K7 quirk, documented in the K7 datasheet (#21016):
> 
> before model 2, the chip was missing two of the pins required for
> proper APIC operation – so the APIC didn't quite work back then
> 
> > BKDG #26094 for K8 Fam Fh DDR1 documents 4 extended LVTs.
> 
> I mis-read that one – correction – it's 0 there, not 4
> 
> also, supposedly no bit 31 = 1 in the version register, but does have
> registers 400h and 410h (but not the other/later extended registers)
> 
> > BKDG #32559 for K8 Fam Fh DDR2 documents 1 extended LVT.
> > BKDG #41256 for K8 Fam 11h (LG) documents 4 extended LVTs.
> >
> > Fam 10h/12h, 14h and 16h, and 15h all have 4 – no surprises.
> >
> > The Fam 10h BKDG (#31116) has an explicit entry in its "Major
> > Changes Relative to Family 0Fh Processors" section: "Number
> > of extended LVT interrupts in APIC increased to 4." – AMD may
> > want to clarify what was correct vs not for those old K8 models.
> 
> per the correction above – K8 went from 0 to 1 to 4 extended LVTs

Right, I looked up what I could. The fallback below is explicitly for 
addressing those.

> 
> > > + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> > > + apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
> >
> > This seems... unsafe?
> 
> double-check it w.r.t. K7 and K8 Fam Fh DDR1, please

This fallback exists purely to retain the current default (except that 
it is now restricted to AMD processors)

The default being 4 (rather than 1 or even 0) is not really an issue 
because this function won't be invoked for older processors.  The common 
case is for this to be invoked with a BIOS-provided offset.  The only 
exception is for IBS for family 0x10, but that family has 4 extended 
LVTs present (see ibs_eilvt_setup()).


- Naveen