Re: [PATCH net 2/2] dt-bindings: net: updated interrupt type to be active low, level triggered

[Krzysztof Kozlowski]

On Fri, May 15, 2026 at 06:40:45PM +0200, Andrew Lunn wrote:
> > Also, did you consider the board layout?
> 
> Hum. How would a board design convert a level interrupt into an edge
> interrupt?

I don't know how feasible or useful in practice, but such converters in
theory are simple:

1. RC differentiator + Schmitt trigger
2. Logic-gate edge detector
3. Monostable (“one-shot”) pulse generator
4. Flip-flop / synchronizer logic in CPLD/FPGA/MCU
5. Dedicated interrupt-controller or GPIO expander ICs

Different point is that Rob said these flags should represent what the
device expects. I disagree with that, because except RC delay GPIO
bindings, we do not have representation of any inverters, thus this flag
should rather represent the final board layout.

> 
> Use the level signal to gate a clock signal? So while the interrupt is
> low, you get a stream of edges? Does that really exist?
> 
>      Andrew