Re: [PATCH v2 1/4] dt-bindings: firmware: qcom,scm: Add minidump SRAM property
From: Mukesh Ojha
Date: Fri May 22 2026 - 03:58:35 EST
On Wed, May 20, 2026 at 12:17:21PM +0200, Krzysztof Kozlowski wrote:
> On Tue, May 19, 2026 at 10:44:39PM +0530, Mukesh Ojha wrote:
> > On most Qualcomm SoCs where minidump is supported, a word in always-on
> > SRAM is shared between the kernel and boot firmware. Before DDR is
> > initialised on the warm reset following a crash, firmware reads this
> > word to decide if minidump is enabled and collect a minidump and where
> > to deliver it (USB upload to a host, or save to local storage).
> >
> > Add a 'sram' property to the SCM binding to describe a region in
> > always-on SRAM where the minidump download destination value could be
> > written. Boot firmware reads it before DDR is initialised on a warm
> > reset to decide where to store the minidump either to host PC or to
> > on device storage.
> >
> > Signed-off-by: Mukesh Ojha <mukesh.ojha@xxxxxxxxxxxxxxxx>
> > ---
> > .../devicetree/bindings/firmware/qcom,scm.yaml | 16 ++++++++++++++++
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> > index 25f62bacbc91..27422d00b8fc 100644
> > --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> > +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
> > @@ -129,6 +129,13 @@ properties:
> > - description: offset of the download mode control register
> > description: TCSR hardware block
> >
> > + sram:
> > + description:
> > + Phandle to a region in always-on SRAM used to store the download
> > + mode value for boot firmware to read before DDR is initialised on
> > + the next warm reset.
> > + maxItems: 1
> > +
> > allOf:
> > # Clocks
> > - if:
> > @@ -250,3 +257,12 @@ examples:
> > clock-names = "core", "bus", "iface";
> > };
> > };
> > +
> > + - |
> > + firmware {
> > + scm {
> > + compatible = "qcom,scm-kaanapali", "qcom,scm";
>
> Incomplete, missing interrupts.
Interrupt number comes from firmware and has not even been described
statically for SCM for any SoC and so I am not sure to include it in
the example. Perhaps I took the wrong example here and should have taken
some pre-Gunyah Qualcomm SoC.
>
> Best regards,
> Krzysztof
>
--
-Mukesh Ojha