RE: [PATCH 00/17] Add Renesas RZ/G3L SD/eMMC support

[Biju Das]

Hi Wolfram,

Thanks for the feedback.

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Sent: 02 June 2026 22:02
> Subject: Re: [PATCH 00/17] Add Renesas RZ/G3L SD/eMMC support
> 
> On Sat, May 30, 2026 at 05:07:54PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > RZ/G3L SoC has:
> >
> > Channel 0 supports SD and eMMC (including HS400/HS400ES).
> > Channel 1 supports SD and eMMC (except for HS400).
> > Channel 2 supports SD.
> >
> > The SoC supports a maximum frequency of 150 MHz. The SD0 interface
> > does not support IOVS and PWEN in the SDHI register (no internal
> > regulator), unlike SD1 and SD2. It has an internal divider for all modes except HS400.
> > It also has a 2048-bit divider compared to 512 on others. Moreover
> > RZ/G3L supports HS400 enhanced strobe mode.
> 
> Sigh, so many HW changes again...
> 
> I want to review it but I won't have time before the next merge window ends. In the meantime, could
> you resend the series properly in just one thread, please? From patch 14 on, it gets messy...


Sorry about that. I will send v2 with tags collected for binding patch.

Cheers,
Biju