Re: [PATCH v2 2/8] x86/cpu: Get LLC ID for Hygon family 18h model 4h

[Fu Hao]

On 6/3/2026 11:17 AM, Borislav Petkov wrote:
> On Tue, Apr 07, 2026 at 04:23:09PM +0800, Fu Hao wrote:
> > Add support to calculate LLC ID from the number of threads sharing
> > the cache for Hygon family 18h model 4h processor.
> >
> > Signed-off-by: Fu Hao <fuhao@xxxxxxxxxxxxxx>
> > ---
> >   arch/x86/kernel/cpu/cacheinfo.c | 22 +++++++++++++++++-----
> >   1 file changed, 17 insertions(+), 5 deletions(-)
>
> If you're going to copy code at least try to share functionality which is
> kinda begging to be a separate function.
>
> Ontop of yours and untested:
>
> diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
> index 98862afc4e55..8e51226aee74 100644
> --- a/arch/x86/kernel/cpu/cacheinfo.c
> +++ b/arch/x86/kernel/cpu/cacheinfo.c
> @@ -305,10 +305,19 @@ static unsigned int get_cache_id(u32 apicid, const struct _cpuid4_info *id4)
>   	return apicid >> index_msb;
>   }
>   
> +/* LLC ID is calculated from the number of threads sharing the L3 cache. */
> +static void __calc_llc_id(struct cpuinfo_x86 *c)
> +{
> +	u32 llc_index = find_num_cache_leaves(c) - 1;
> +	struct _cpuid4_info id4 = {};
> +
> +	if (!amd_fill_cpuid4_info(llc_index, &id4))
> +		c->topo.llc_id = get_cache_id(c->topo.apicid, &id4);
> +}
> +
>   /*
>    * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist.
>    */
> -
>   void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
>   {
>   	if (!cpuid_amd_hygon_has_l3_cache())
> @@ -324,15 +333,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id)
>   		 */
>   		c->topo.llc_id = c->topo.apicid >> 3;
>   	} else {
> -		/*
> -		 * Newer families: LLC ID is calculated from the number
> -		 * of threads sharing the L3 cache.
> -		 */
> -		u32 llc_index = find_num_cache_leaves(c) - 1;
> -		struct _cpuid4_info id4 = {};
> -
> -		if (!amd_fill_cpuid4_info(llc_index, &id4))
> -			c->topo.llc_id = get_cache_id(c->topo.apicid, &id4);
> +		__calc_llc_id(c);
>   	}
>   }
>   
> @@ -342,15 +343,7 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c)
>   		return;
>   
>   	if (c->x86_model >= 0x4) {
> -		/*
> -		 * From model 4h: LLC ID is calculated from the number
> -		 * of threads sharing the L3 cache.
> -		 */
> -		u32 llc_index = find_num_cache_leaves(c) - 1;
> -		struct _cpuid4_info id4 = {};
> -
> -		if (!amd_fill_cpuid4_info(llc_index, &id4))
> -			c->topo.llc_id = get_cache_id(c->topo.apicid, &id4);
> +		__calc_llc_id(c);
>   	} else {
>   		/*
>   		 * The others are similar to AMD Family 17h up to 1F models: LLC is

Hi Boris,

    Thanks for your guidance. The goal here was to keep the changes
minimal and consistent with the existing code flow. Since Hygon reports
the same CPUID leaves as AMD, it made sense to just follow AMD's current
implementation rather than introduce a separate path.

    For Hygon processors, the LLC ID comes from fixed bit positions
regardless of whether SMT is enabled or not. Therefore, perhaps I could
implement it as follows:

@@ -341,11 +341,18 @@ void cacheinfo_hygon_init_llc_id(struct 
cpuinfo_x86 *c)
        if (!cpuid_amd_hygon_has_l3_cache())
                return;

-       /*
-        * Hygons are similar to AMD Family 17h up to 1F models: LLC is
-        * at the core complex level.  Core complex ID is ApicId[3].
-        */
-       c->topo.llc_id = c->topo.apicid >> 3;
+       switch (c->x86_model) {
+       case 0x6:
+               c->topo.llc_id = c->topo.apicid >> 4;
+               break;
+       case 0x7:
+       case 0x8:
+               c->topo.llc_id = c->topo.apicid >> 5;
+               break;
+       default:
+               c->topo.llc_id = c->topo.apicid >> 3;
+               break;
+       }
 }

Thank you again for reviewing and offering your suggestions.

--
Regards,
Fu Hao