[PATCH 1/5] arm64: dts: renesas: r9a09g077: Add VSPD and FCPVD nodes
From: Prabhakar
Date: Tue Jun 09 2026 - 08:57:13 EST
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Add VSPD and FCPVD nodes to RZ/T2H SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 40494159831d..dda7008acdd9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -1376,6 +1376,28 @@ sdhi1_vqmmc: vqmmc-regulator {
status = "disabled";
};
};
+
+ fcpvd: fcp@920d0000 {
+ compatible = "renesas,r9a09g077-fcpvd", "renesas,fcpv";
+ reg = <0 0x920d0000 0 0x10000>;
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
+ <&cpg CPG_MOD 1204>,
+ <&cpg CPG_CORE R9A09G077_LCDC_CLKD>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ };
+
+ vspd: vsp@920e0000 {
+ compatible = "renesas,r9a09g077-vsp2", "renesas,r9a07g044-vsp2";
+ reg = <0 0x920e0000 0 0x8000>;
+ interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>,
+ <&cpg CPG_MOD 1204>,
+ <&cpg CPG_CORE R9A09G077_LCDC_CLKD>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ renesas,fcp = <&fcpvd>;
+ };
};
stmmac_axi_setup: stmmac-axi-config {
--
2.54.0