Re: [PATCH] pci: loongson: Avoid L0s on LS7A1000 PCIe x8 [0014:7a29] Root Ports rev2

[Mingcong Bai]

Hi Ruoyao,

在 2026/6/9 23:25, Xi Ruoyao 写道:
> Commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> devicetree platforms") has broke booting of a Loongson 3B4000 + 7A1000
> server with an Intel 750 Series SSD.  We also found a Loongson 3A5000
> board using the same 7A1000 bridge chip exhibiting the same issue with
> pcie_aspm=force and pcie_aspm.policy=powersave (ASPM is not enabled by
> default on the 3A5000 board because it's based on ACPI and the _OSC
> method has not been implemented in its DSDT/SSDT yet).
>
> This seems only affecting the 7A1000 chips shipping the revision 2 of
> the PCIe x8 Root Port: on other two boards with a (persumably older)
> LS7A1000 bridge chip utilizing the revision 1 of the root port, the
> issue does not reproduce.
Tested good on a Lemote A1906 (dual Loongson 3B4000), which failed to 
boot with an Intel 750 with kernel versions >= 6.18.0.

Tested-by: Mingcong Bai <jeffbai@xxxxxxx>

Best Regards,
Mingcong Bai