Re: [Patch v2 7/9] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS
From: Mi, Dapeng
Date: Wed Jun 10 2026 - 05:07:05 EST
On 6/10/2026 4:20 PM, Peter Zijlstra wrote:
> On Tue, Jun 09, 2026 at 01:02:20PM +0800, Dapeng Mi wrote:
>> On SPR guests where pebs_baseline is not advertised, running:
>>
>> $ ./perf record -e cpu/event=0x00,umask=0x01,i\
>> name=INST_RETIRED.PREC_DIST/p -c 10000 sleep 1
>>
>> can trigger:
>>
>> unchecked MSR access error: WRMSR to 0x3f1 ... in\
>> intel_pmu_pebs_enable_all()
>>
>> Root cause:
>> SPR-specific PEBS constraints allow fixed-counter scheduling,
>> for example INST_RETIRED.PREC_DIST on fixed counter 0. In guests without
>> pebs_baseline, KVM does not support PEBS sampling on fixed counters,
>> so enabling such events reaches an invalid MSR programming path.
>>
>> Fix:
>> Drop fixed-counter entries from the PEBS constraint table. Without
>> pebs_baseline, those fixed-counter PEBS events now resolve to empty
>> constraints and are not scheduled/enabled, avoiding the warning and the
>> broken guest PEBS path.
>>
>> This is safe because, in pebs_baseline-capable cases, PEBS constraint
>> lookup already falls back to non-PEBS constraints when needed, and
>> fixed-counter constraints are effectively shared there.
> I am confused, this works outside of KVM? (It appears to work fine on my
> spr).. so removing this to fix some guest only issue seems wrong.
The reason that it works on bare metal is currently the constraint lookup
would fallback into non-PEBS constraints if there is no matched entry in
the PEBS constraints as long as the PEBS supports sampling on all counters
including fixed counters (what the flag "PMU_FL_PEBS_ALL" indicates), like
the below code shows.
```
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
{
struct event_constraint *pebs_constraints = hybrid(event->pmu,
pebs_constraints);
struct event_constraint *c;
if (!event->attr.precise_ip)
return NULL;
if (pebs_constraints) {
for_each_event_constraint(c, pebs_constraints) {
if (constraint_match(c, event->hw.config)) {
event->hw.flags |= c->flags;
return c;
}
}
}
/*
* Extended PEBS support
* Makes the PEBS code search the normal constraints.
*/
if (x86_pmu.flags & PMU_FL_PEBS_ALL)
return NULL;
return &emptyconstraint;
}
static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
struct perf_event *event)
{
struct event_constraint *c;
c = intel_vlbr_constraints(event);
if (c)
return c;
c = intel_bts_constraints(event);
if (c)
return c;
c = intel_shared_regs_constraints(cpuc, event);
if (c)
return c;
c = intel_pebs_constraints(event);
if (c)
return c;
return x86_get_event_constraints(cpuc, idx, event);
}
```
if intel_pebs_constraints() can't find the matched entry from PEBS
constraints and PMU_FL_PEBS_ALL is set, NULL would be returned and it would
lead to fallback the non-PEBS constraints lookup.
>From Icelake starts, regardless of the extended PEBS or the arch-PEBS, all
counters including the fixed counters support PEBS sampling and the
flag PMU_FL_PEBS_ALL would set by default.
Since the non-PEBS constraints contain the similar fixed counter
constraints, the fixed counter events would still be correctly scheduled on
the fixed counters.
for example, here is the fixed counter constraints in
intel_icl_event_constraints[],
```
static struct event_constraint intel_icl_event_constraints[] = {
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
......
```
>
>
>> Reported-by: Yi Lai <yi1.lai@xxxxxxxxx>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>
>> ---
>> arch/x86/events/intel/ds.c | 13 -------------
>> 1 file changed, 13 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index cb72af9b61ce..5db15a92017a 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -1447,10 +1447,6 @@ struct event_constraint intel_skl_pebs_event_constraints[] = {
>> };
>>
>> struct event_constraint intel_icl_pebs_event_constraints[] = {
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
>> -
>> INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
>> INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
>> INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
>> @@ -1473,9 +1469,6 @@ struct event_constraint intel_icl_pebs_event_constraints[] = {
>> };
>>
>> struct event_constraint intel_glc_pebs_event_constraints[] = {
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
>> -
>> INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
>> INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
>> INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
>> @@ -1500,9 +1493,6 @@ struct event_constraint intel_glc_pebs_event_constraints[] = {
>> };
>>
>> struct event_constraint intel_lnc_pebs_event_constraints[] = {
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
>> -
>> INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1), /* OCR.* events */
>> INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1), /* OCR.* events */
>>
>> @@ -1534,9 +1524,6 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {
>> };
>>
>> struct event_constraint intel_pnc_pebs_event_constraints[] = {
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
>> - INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
>> -
>> INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc),
>> INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
>> INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
>> --
>> 2.34.1
>>