[PATCH v1 4/6] ASoC: qcom: q6prm: add Audio IF clock IDs
From: Prasad Kumpatla
Date: Wed Jun 10 2026 - 12:26:47 EST
Add the q6prm clock table entries and internal DSP clock IDs for LPASS
Audio IF backend clocks.
The public binding IDs map to q6prm DSP clock IDs starting at 0x500 for
Audio IF0 IBIT/EBIT. Add the internal definitions and register all Audio
IF IBIT and EBIT clocks so machine drivers can request them through the
APM clock controller.
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@xxxxxxxxxxxxxxxx>
---
sound/soc/qcom/qdsp6/q6prm-clocks.c | 28 ++++++++++++++++++++++++++++
sound/soc/qcom/qdsp6/q6prm.h | 29 +++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c
index 51b131fa9..b6755da6a 100644
--- a/sound/soc/qcom/qdsp6/q6prm-clocks.c
+++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c
@@ -64,6 +64,34 @@ static const struct q6dsp_clk_init q6prm_clks[] = {
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF0_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF0_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF1_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF1_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF2_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF2_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF3_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF3_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF4_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF4_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF5_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF5_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF6_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF6_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF7_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF7_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF8_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF8_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF9_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF9_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF10_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF10_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF11_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF11_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF12_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_INTF12_EBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_VA_INTF0_IBIT),
+ Q6PRM_CLK(LPASS_CLK_ID_AUD_VA_INTF0_EBIT),
Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
"LPASS_HW_MACRO"),
Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
index 7b751486c..c1838d80c 100644
--- a/sound/soc/qcom/qdsp6/q6prm.h
+++ b/sound/soc/qcom/qdsp6/q6prm.h
@@ -98,6 +98,35 @@
/* Clock ID for RX CORE MCLK2 2X MCLK */
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF0_IBIT 0x500
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF0_EBIT 0x501
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF1_IBIT 0x502
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF1_EBIT 0x503
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF2_IBIT 0x504
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF2_EBIT 0x505
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF3_IBIT 0x506
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF3_EBIT 0x507
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF4_IBIT 0x508
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF4_EBIT 0x509
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF5_IBIT 0x50A
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF5_EBIT 0x50B
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF6_IBIT 0x50C
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF6_EBIT 0x50D
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF7_IBIT 0x50E
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF7_EBIT 0x50F
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF8_IBIT 0x510
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF8_EBIT 0x511
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF9_IBIT 0x512
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF9_EBIT 0x513
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF10_IBIT 0x514
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF10_EBIT 0x515
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF11_IBIT 0x516
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF11_EBIT 0x517
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF12_IBIT 0x518
+#define Q6PRM_LPASS_CLK_ID_AUD_INTF12_EBIT 0x519
+#define Q6PRM_LPASS_CLK_ID_AUD_VA_INTF0_IBIT 0x550
+#define Q6PRM_LPASS_CLK_ID_AUD_VA_INTF0_EBIT 0x551
+
#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
#define Q6PRM_HW_CORE_ID_LPASS 1
--
2.34.1