[PATCH v2 3/3] cpufreq: ACPI: Avoid racy updates to MSR_K7_HWCR in boost_set_msr()

[Jim Mattson]

On AMD and Hygon CPUs, use amd_update_hwcr() in boost_set_msr() so that all
runtime updates of MSR_K7_HWCR go through the common interrupt-safe helper.

boost_set_msr() usually runs with interrupts disabled, but the call via
cpufreq_boost_down_prep() on the cpufreq policy teardown path runs in
process context with interrupts enabled. The MCE injector's
toggle_hw_mce_inject() modifies the same MSR via a crosscall that can
target any CPU. If such a crosscall lands between the open-coded read and
write of MSR_K7_HWCR, the injector's McStatusWrEn update is lost.

Suggested-by: Borislav Petkov <bp@xxxxxxxxx>
Fixes: 21690934d934 ("EDAC, mce_amd_inj: Enable direct writes to MCE MSRs")
Signed-off-by: Jim Mattson <jmattson@xxxxxxxxxx>
---
 drivers/cpufreq/acpi-cpufreq.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 21639d9ac753..8fc4cfd045c4 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -103,9 +103,10 @@ static int boost_set_msr(bool enable)
 		break;
 	case X86_VENDOR_HYGON:
 	case X86_VENDOR_AMD:
-		msr_addr = MSR_K7_HWCR;
-		msr_mask = MSR_K7_HWCR_CPB_DIS;
-		break;
+		if (enable)
+			return amd_update_hwcr(MSR_K7_HWCR_CPB_DIS, 0);
+		else
+			return amd_update_hwcr(0, MSR_K7_HWCR_CPB_DIS);
 	default:
 		return -EINVAL;
 	}
-- 
2.54.0.1136.gdb2ca164c4-goog