Re: [PATCH v6 02/11] ARM: dts: renesas: r8a7740: Add clocks for FSI

[Bui Duc Phuc]

Hi

>
> Thanks, confirmed.
> Have a nice weekend!
>

I went through the schematics and summarized the FSIA clock and data
routing below.
This is mostly for future reference, so that anyone investigating this
hardware setup later
can quickly understand the default configuration without having to
revisit the schematics.

In summary, the current hardware connection between FSIA and the
WM8978 codec is
configured as follows:

Master Clock (MCLK)

Pin 11 (MCLK) of the codec is connected to pin 3 of OSC X8, which
provides the 12.288 MHz clock source,
and is also connected to the R8A7740.On the R8A7740 side, there are
two possible routing options:
1 . Pin G3 (FSIACK - Master Clock Input for PORTA) through resistor R250.
     R250 is a 0-ohm resistor and is currently populated.
2. Pin K5 (FSIAOMC - Master Clock Output for PORTA) through resistor R120.
    R120 is a 0-ohm resistor but is currently not populated.

=> With the default hardware configuration, the master clock is
supplied by OSC X8 and FSIA operates in slave mode.

Bit Clock (BCLK)

Pin 8 of the codec is connected to the R8A7740.
On the R8A7740 side, there are two possible routing options:

1. Pin L5 (FSIAIBT - Sound Input Bit Clock, slave) through resistor R123.
     R123 is a 0-ohm resistor and is currently populated.

2. Pin F2 (FSIAOBT - Sound Output Bit Clock, master) through resistor R139.
    R139 is a 0-ohm resistor but is currently not populated.
=> With the default hardware configuration, FSIA operates in slave
mode and receives the bit clock from the codec.

LR Clock (LRCLK)

Pin 7 of the codec is connected to the R8A7740.
On the R8A7740 side, there are two possible routing options:
1. Pin F1 (FSIAILR - Sound Input LR Clock, slave) through resistor R124.
   R124 is a 0-ohm resistor and is currently populated.
2. Pin E2 (FSIAOLR - Sound Output LR Clock, master) through resistor R227.
   R227 is a 0-ohm resistor but is currently not populated.
=> With the default hardware configuration, FSIA operates in slave
mode and receives the LR clock from the codec.

Input Data

Pin 9 (ADCDAT) of the codec is connected to pin H4 (FSIAISLD - Sound
Input Serial Data) of the R8A7740
through the DBGMD/LCDC0/FSIA mux path.

Output Data

Pin 10 (DACDAT) of the codec is connected directly to pin J4 (FSIAOSLD
- Sound Output Serial Data) of the R8A7740.

Conclusion

With the current default hardware configuration:
The WM8978 codec operates as the clock master. FSIA operates as the clock slave.
If we want to test FSIA in master mode, the resistor configuration for
all clock lines must be changed:

1.Master Clock (MCLK)
2.Bit Clock (BCLK)
3.LR Clock (LRCLK)

In other words, all clock routing selections currently connected to
the slave-side pins must be
switched to the corresponding master-side pins.

Best regards,
Phuc