Re: [PATCH v1 2/4] arm64: dts: qcom: sm8550: Add JPEG encoder node

[Dmitry Baryshkov]

On Fri, Jun 12, 2026 at 10:44:15PM +0300, Atanas Filipov wrote:
> Add the missing JPEG encoder hardware node in SM8550 DTS so the
> new qcom-jpeg V4L2 encoder driver can bind and operate on this
> platform.
> 
> The node wires the resources expected by the binding and driver,
> including clocks, power domain, IOMMUs and interconnect paths.
> 
> Signed-off-by: Atanas Filipov <atanas.filipov@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 42 ++++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6..8090b8b1d7bd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3677,6 +3677,48 @@ port@7 {
>  			};
>  		};
>  
> +		qcom_jpeg_enc: jpeg-encoder@ac4e000 {

To reiterate and reinforce what others wrote: this should be a subdevice
under the isp@ or camss@ node.

Then, drop the label, please.


> +			cell-index = <0>;

No cell-index.

> +			compatible = "qcom,sm8550-jenc";
> +
> +			reg = <0 0xac4e000 0 0x4000>;

0x0 instead of 0, pad address to 8 digits (0x0ac4e000).

> +			reg-names = "jpeg";

No need to name the only region.

> +
> +			interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING 0>;
> +			power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> +			clocks = <&gcc GCC_CAMERA_HF_AXI_CLK>,
> +				 <&gcc GCC_CAMERA_SF_AXI_CLK>,
> +				 <&camcc CAM_CC_CORE_AHB_CLK>,
> +				 <&camcc CAM_CC_CPAS_AHB_CLK>,
> +				 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> +				 <&camcc CAM_CC_JPEG_CLK>;
> +
> +			clock-names = "gcc_hf_axi",
> +				      "gcc_sf_axi",
> +				      "core_ahb",
> +				      "cpas_ahb",
> +				      "camnoc_axi",
> +				      "jpeg";
> +
> +			iommus = <&apps_smmu 0x20C0 0x20>,
> +				 <&apps_smmu 0x20E0 0x20>;

lowercase the hex.

> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 0
> +					 &config_noc SLAVE_CAMERA_CFG 0>,

Use tags instead of 0.

> +					<&mmss_noc MASTER_CAMNOC_HF 0
> +					 &mc_virt SLAVE_EBI1 0>,
> +					<&mmss_noc MASTER_CAMNOC_SF 0
> +					 &mc_virt SLAVE_EBI1 0>,
> +					<&mmss_noc MASTER_CAMNOC_ICP 0
> +					 &mc_virt SLAVE_EBI1 0>;
> +
> +			interconnect-names = "cam_ahb",
> +					     "cam_hf_0_mnoc",
> +					     "cam_sf_0_mnoc",
> +					     "cam_sf_icp_mnoc";

I know that camera settled on these names. Please use a better approach:
describe the source and the destination of the interconnect (see how
other devices name them).

> +		};
> +
>  		camcc: clock-controller@ade0000 {
>  			compatible = "qcom,sm8550-camcc";
>  			reg = <0 0x0ade0000 0 0x20000>;
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry