[PATCH] Add JEDEC ID table entries for additional ISSI SPI-NOR devices. (QSPI 2026)
From: Jeffrey Yu
Date: Mon Jun 15 2026 - 21:21:36 EST
Add JEDEC ID table entries for additional ISSI SPI-NOR
devices. (QSPI 2026)
These parts previously not yet supported.
With these entries, Linux software can match the device by JEDEC ID
and use the existing ISSI SPI-NOR device handling.
Newly added devices include:
- IS25LP010E (JEDEC 0x9d4011)
https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
- IS25LP020E (JEDEC 0x9d4012)
https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
- IS25LP040E (JEDEC 0x9d4013)
https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
- IS25WP020E (JEDEC 0x9d7012)
https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
- IS25WP040E (JEDEC 0x9d7013)
https://www.issi.com/WW/pdf/25LP-WP040E-020E-010E-512E-025E.pdf
- IS25WJ032F (JEDEC 0x9d7016)
https://www.issi.com/WW/pdf/25WJ032F.pdf
- IS25WJ064F (JEDEC 0x9d7117)
https://www.issi.com/WW/pdf/25WJ064F.pdf
- IS25WJ128F (JEDEC 0x9d7118)
https://www.issi.com/WW/pdf/25WJ128F.pdf
- IS25LP512MJ (JEDEC 0x9d6020)
https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf
- IS25WP512MJ (JEDEC 0x9d7020)
https://www.issi.com/WW/pdf/25LP-WP512MJ.pdf
- IS25LP01GJ (JEDEC 0x9d6021)
https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf
- IS25LP01GG (JEDEC 0x9d6021)
https://www.issi.com/WW/pdf/25LP-WP01GG.pdf
- IS25WP01GJ (JEDEC 0x9d7021)
https://www.issi.com/WW/pdf/25LP-WP01GJ.pdf
- IS25WP01GG (JEDEC 0x9d7021)
https://www.issi.com/WW/pdf/25LP-WP01GG.pdf
- IS25LP02GJ (JEDEC 0x9d6022)
https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf
- IS25WP02GJ (JEDEC 0x9d7022)
https://www.issi.com/WW/pdf/25LP-WP02GJ.pdf
- IS25LP02GG (JEDEC 0x9d6022)
https://www.issi.com/WW/pdf/25LP-WP02GG.pdf
- IS25WP02GG (JEDEC 0x9d7022)
https://www.issi.com/WW/pdf/25LP-WP02GG.pdf
Signed-off-by: Jeffrey Y <jeyu@xxxxxxxx>
---
drivers/mtd/spi-nor/issi.c | 138 +++++++++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 18d9a00aa22e..a39c254a8a76 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -126,6 +126,144 @@ static const struct flash_info issi_nor_parts[] = {
.flags = SPI_NOR_QUAD_PP,
.fixups = &is25lp256_fixups,
.fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x40, 0x11),
+ .name = "is25lp010e",
+ .size = SZ_1M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x40, 0x12),
+ .name = "is25lp020e",
+ .size = SZ_2M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x40, 0x13),
+ .name = "is25lp040e",
+ .size = SZ_4M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x12),
+ .name = "is25wp020e",
+ .size = SZ_2M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x13),
+ .name = "is25wp040e",
+ .size = SZ_4M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x16),
+ .name = "is25wj032f",
+ .size = SZ_32M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x71, 0x17),
+ .name = "is25wj064f",
+ .size = SZ_64,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x71, 0x18),
+ .name = "is25wj128f",
+ .size = SZ_128M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x20),
+ .name = "is25lp512mj",
+ .size = SZ_512M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x20),
+ .name = "is25wp512mj",
+ .size = SZ_512M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x21),
+ .name = "is25lp01gj",
+ .size = SZ_1G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x21),
+ .name = "is25lp01gg",
+ .size = SZ_1G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x21),
+ .name = "is25wp01gj",
+ .size = SZ_1G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x21),
+ .name = "is25wp01gg",
+ .size = SZ_1G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x22),
+ .name = "is25lp02gj",
+ .size = SZ_2G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x22),
+ .name = "is25wp02gj",
+ .size = SZ_2G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ }, {
+ .id = SNOR_ID(0x9d, 0x60, 0x22),
+ .name = "is25lp02gg",
+ .size = SZ_2G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
+ }, {
+ .id = SNOR_ID(0x9d, 0x70, 0x22),
+ .name = "is25wp02gg",
+ .size = SZ_2G,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_TB_SR_BIT6,
+ .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
+ .fixup_flags = SPI_NOR_4B_OPCODES,
}
};
--
2.43.0