Re: [PATCH v4 1/6] dt-bindings: display: verisilicon, dc: generalize for single-output variants

[Joey Lu]

On 6/15/2026 4:19 PM, Icenowy Zheng wrote:
> 在 2026-06-15一的 14:49 +0800，Joey Lu写道：
> > The existing schema hard-codes the five-clock/three-reset/dual-port
> > topology of the DC8200 IP block, preventing reuse for single-output
> > variants such as the Verisilicon DCUltraLite used in the Nuvoton
> > MA35D1
> > SoC.
> >
> > Rework the schema so that variant-specific constraints are expressed
> > via
> > allOf/if blocks:
> >
> > - Add nuvoton,ma35d1-dcu to the SoC-specific compatible enum.  The
> >    generic verisilicon,dc fallback remains the driver-binding string.
> > - Move clock and reset items descriptions into the per-variant
> > allOf/if
> >    blocks; keep only minItems/maxItems at the top level so the base
> > schema
> >    accepts all variants.
> > - Restore full items lists for clock-names and reset-names at the top
> >    level with minItems so the names are validated against the
> > descriptions.
> > - Keep ports in the global required list and keep
> > additionalProperties: false.
> > - Add an allOf/if block for thead,th1520-dc8200: five-clock (core,
> > axi,
> >    ahb, pix0, pix1), three-reset (core, axi, ahb), required resets.
> > - Add an allOf/if block for nuvoton,ma35d1-dcu: two-clock (core,
> > pix0),
> >    one-reset (core), required resets.
> >
> > Signed-off-by: Joey Lu <a0987203069@xxxxxxxxx>
> > ---
> >   .../bindings/display/verisilicon,dc.yaml      | 80
> > +++++++++++++++++--
> >   1 file changed, 73 insertions(+), 7 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> > b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> > index 9dc35ab973f2..0c41286b8223 100644
> > --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> > @@ -17,6 +17,7 @@ properties:
> >       items:
> >         - enum:
> >             - thead,th1520-dc8200
> > +          - nuvoton,ma35d1-dcu
> >         - const: verisilicon,dc # DC IPs have discoverable ID/revision
> > registers
> >   
> >     reg:
> > @@ -26,14 +27,12 @@ properties:
> >       maxItems: 1
> >   
> >     clocks:
> > -    items:
> > -      - description: DC Core clock
> > -      - description: DMA AXI bus clock
> > -      - description: Configuration AHB bus clock
> > -      - description: Pixel clock of output 0
> > -      - description: Pixel clock of output 1
> Clock descriptions should still be in the global part instead of the
> per-compatible part.
>
> In the per-compatible part, clock-names should be constraint for SoCs.
I will move the `items:` clock descriptions back into the global 
`clocks:` property, covering all five possible clocks. In the 
per-compatible sections I will remove the description items and only 
constrain `clocks: minItems/maxItems` and `clock-names: 
minItems/maxItems`; for nuvoton,ma35d1-dcu I will additionally override 
`clock-names: items:` to the two names actually used (core, pix0).
> > +    minItems: 2
> > +    maxItems: 5
> >   
> >     clock-names:
> > +    minItems: 2
> > +    maxItems: 5
> >       items:
> >         - const: core
> >         - const: axi
> > @@ -42,12 +41,16 @@ properties:
> >         - const: pix1
> >   
> >     resets:
> > +    minItems: 1
> > +    maxItems: 3
> >       items:
> >         - description: DC Core reset
> >         - description: DMA AXI bus reset
> >         - description: Configuration AHB bus reset
> >   
> >     reset-names:
> > +    minItems: 1
> > +    maxItems: 3
> >       items:
> >         - const: core
> >         - const: axi
> > @@ -59,7 +62,7 @@ properties:
> >       properties:
> >         port@0:
> >           $ref: /schemas/graph.yaml#/properties/port
> > -        description: The first output channel , endpoint 0 should be
> > +        description: The first output channel, endpoint 0 should be
> If you really want to fix this, please make it a separated patch
> instead of doing it here, for commit atomicity.
>
> Thanks,
> Icenowy
I’ll drop this change and keep it as is
> >             used for DPI format output and endpoint 1 should be used
> >             for DP format output.
> >   
> > @@ -77,6 +80,69 @@ required:
> >     - clock-names
> >     - ports
> >   
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: thead,th1520-dc8200
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 5
> > +          maxItems: 5
> > +          items:
> > +            - description: DC Core clock
> > +            - description: DMA AXI bus clock
> > +            - description: Configuration AHB bus clock
> > +            - description: Pixel clock of output 0
> > +            - description: Pixel clock of output 1
> > +
> > +        clock-names:
> > +          minItems: 5
> > +          maxItems: 5
> > +
> > +        resets:
> > +          minItems: 3
> > +          maxItems: 3
> > +
> > +        reset-names:
> > +          minItems: 3
> > +          maxItems: 3
> > +
> > +      required:
> > +        - resets
> > +        - reset-names
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: nuvoton,ma35d1-dcu
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 2
> > +          maxItems: 2
> > +          items:
> > +            - description: DC Core clock
> > +            - description: Pixel clock of output 0
> > +
> > +        clock-names:
> > +          minItems: 2
> > +          maxItems: 2
> > +
> > +        resets:
> > +          minItems: 1
> > +          maxItems: 1
> > +
> > +        reset-names:
> > +          maxItems: 1
> > +
> > +      required:
> > +        - resets
> > +        - reset-names
> > +
> >   additionalProperties: false
> >   
> >   examples: