RE: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC

[Biju Das]

Hi Wolfram,

Thanks for the feedback.

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Sent: 17 June 2026 13:20
> Subject: Re: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
> 
> Hi Biju,
> 
> On Wed, Jun 03, 2026 at 07:57:01AM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI
> > controller is similar to RZ/G2L but has five clocks (core, clkh, cd,
> > aclk, aclkm) and three resets (rst, axim, axis), so update the
> > clocks/clock-names maximum to 5 and resets/reset-names maximum to 3.
> > It has an internal divider for all modes except HS400, and a 2048-bit
> > divider compared to 512 on others.
> >
> > Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> I know you work on v18 already, but some high level remarks already.

OK.

> 
> > +              - description: ACLK/IACLKS, SDHI channel bus clock.
> > +              - description: IACLKM, SDHI channel bus clock m.
> 
> What does 's' and 'm' stand for? Is it mentioned in the docs? Would be nice to have here as well, if so.

I know only it is bus clocks. But don't know what is 'bus clock s' and 'bus clock m' stands for.
It could be just clock name.

I will check this with hardware/documentation team and update you.

As per the clock excel sheet,:

SDHI0_IMCLK: "SDHI ch0  main clock 1"
		After supplying this clock to SDHI ch0, it is possible to divide the frequency on the SDHI ch0 side and output the 		clock to the outside.

SDHI0_IMCLK2: "SDHI ch0  main clock 2"
		Input is always required even when suspending.
		When this clock is turned off, external SD card connection (Card Detect) cannot be detected."

SDHI0_CLK_HS: "SDHI ch0  High speed clock
		This clock always operates with a relationship of 2 times that of SDHI ch0 main clock 1.
		Must be supplied when using SDR104, HS200.
		It can be stopped when suspended. "

SDHI0_IACLKS: "SDHI ch0 bus clock
		It can be stopped when suspended. "

SDHI0_IACLKM: "SDHI ch0 bus clock
		It can be stopped when suspended. "

> 
> > +          resets:
> > +            items:
> > +              - description: rst, Core reset.
> > +              - description: axim, SDHI axi bus reset m.
> > +              - description: axis, SDHI axi bus reset s.
> 
> Ditto.

The reset signal mentioned in the hardware manual are
SDHIx_IXRST, SDHIx_IXRSTAXIM and SDHIx_IXRSTAXIS (where x=0,1,2)

I will check this as well with hardware/documentation team and update you.

Cheers,
Biju

> 
> Happy hacking,
> 
>    Wolfram