Re: [PATCH 4/7] KVM: arm64: Set IL for injected FPAC exceptions during ERET emulation

[Marc Zyngier]

On Sun, 14 Jun 2026 17:33:33 +0100,
Fuad Tabba <tabba@xxxxxxxxxx> wrote:
> 
> The FPAC syndrome constructed during nested ERET emulation does not set
> IL. For FPAC (EC=0x1C), IL reflects the instruction length. ERET and
> its authenticated variants are always A64 32-bit instructions, so IL
> must be 1.
> 
> Fixes: 213b3d1ea161 ("KVM: arm64: nv: Handle ERETA[AB] instructions")
> Signed-off-by: Fuad Tabba <tabba@xxxxxxxxxx>
> ---
>  arch/arm64/kvm/emulate-nested.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index dba7ced74ca5..4b39363cf891 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -2777,7 +2777,7 @@ void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu)
>  		 */
>  		if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) {
>  			esr &= ESR_ELx_ERET_ISS_ERETA;
> -			esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC);
> +			esr |= FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_FPAC) | ESR_ELx_IL;

In general, I prefer retaining information that is present in the
source exception, rather than adding arbitrary bits without much
context, even if we only support AArch64 for NV. In this case, I'd
rather see this:

			esr &= (ESR_ELx_ERET_ISS_ERETA | ESR_ELx_IL);

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.