Re: [PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller

[Philipp Zabel]

On Do, 2026-06-18 at 09:27 +0000, Joakim  Zhang wrote:
> Hello,
> 
> 
> > -----Original Message-----
> > From: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> > Sent: Thursday, June 18, 2026 4:30 PM
> > To: Joakim Zhang <joakim.zhang@xxxxxxxxxxx>; Conor Dooley
> > <conor@xxxxxxxxxx>
> > Cc: mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; bmasney@xxxxxxxxxx;
> > robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; Gary Yang
> > <Gary.Yang@xxxxxxxxxxx>; cix-kernel-upstream <cix-kernel-
> > upstream@xxxxxxxxxxx>; linux-clk@xxxxxxxxxxxxxxx;
> > devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm-
> > kernel@xxxxxxxxxxxxxxxxxxx
> > Subject: Re: [PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss
> > clock controller
> > 
> > EXTERNAL EMAIL
> > 
> > CAUTION: Suspicious Email from unusual domain.
> > 
> > On Do, 2026-06-18 at 01:43 +0000, Joakim  Zhang wrote:
> > > Hello,
> > > 
> > > 
> > > > -----Original Message-----
> > > > From: Conor Dooley <conor@xxxxxxxxxx>
> > > > Sent: Wednesday, June 17, 2026 11:56 PM
> > > > To: Joakim Zhang <joakim.zhang@xxxxxxxxxxx>
> > > > Cc: mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; bmasney@xxxxxxxxxx;
> > > > robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> > > > p.zabel@xxxxxxxxxxxxxx; Gary Yang <gary.yang@xxxxxxxxxxx>;
> > > > cix-kernel- upstream <cix-kernel-upstream@xxxxxxxxxxx>;
> > > > linux-clk@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> > > > linux-kernel@xxxxxxxxxxxxxxx; linux-arm- kernel@xxxxxxxxxxxxxxxxxxx
> > > > Subject: Re: [PATCH v4 3/5] dt-bindings: clock:
> > > > cix,sky1-audss-clock: add audss clock controller
> > > > 
> > > > On Wed, Jun 17, 2026 at 02:04:35PM +0800, joakim.zhang@xxxxxxxxxxx
> > wrote:
> > > > > From: Joakim Zhang <joakim.zhang@xxxxxxxxxxx>
> > > > > 
> > > > > The AUDSS CRU contains an internal clock tree of muxes, dividers
> > > > > and gates for DSP, I2S, HDA, DMAC and related blocks. The clock
> > > > > provider is a child node of the cix,sky1-audss-system-control
> > > > > syscon and accesses registers through the parent MMIO region.
> > > > 
> > > > Why can this not just be part of the parent syscon node?
> > > 
> > > The clock and reset blocks are handled by different subsystems and
> > maintainers (clk vs reset). Putting the clock provider on the parent syscon node
> > would mean a single driver has to register both the reset controller and the
> > clock provider on one device, which doesn't fit well.
> > 
> > There are many examples of clock and reset drivers sharing the same node, by
> > using platform_driver for one (usually clk) and auxiliary_driver for the other
> > (usually reset).
> 
> OK, I will have a look.  If you are also prefer to this, I will refactor the patch.

The hardware should dictate this, not the driver/subsystem/maintainer
boundaries. Looking at the register numbers used by the drivers, and
assuming that the audss_cru label in the dts patch means the TRM also
calls this a single Clock-Reset-Unit, I'd say Conor has a point.

regards
Philipp