Re: [PATCH] clk: canaan: Clear rate fields before reprogramming dividers

[Brian Masney]

On Thu, Jun 18, 2026 at 05:50:30AM +0100, David Carlier wrote:
> The rate set_rate helpers perform a read-modify-write on the divider
> and multiplier registers but only ever OR the new value in, without
> first masking off the existing field. The first write after reset lands
> on a zeroed field and looks correct, but any later reprogramming leaves
> the old bits set: the field becomes the bitwise OR of the previous and
> new encodings, corrupting the divider or multiplier.
> 
> Mask off each field before writing the new value so reprogramming a
> clock to a different rate produces the intended register contents.
> 
> Fixes: a7b7c7c6c016 ("clk: canaan: Add clock driver for Canaan K230")
> Signed-off-by: David Carlier <devnexen@xxxxxxxxx>

Reviewed-by: Brian Masney <bmasney@xxxxxxxxxx>