Re: [PATCH 1/1] drm/amd/display: set MSA MISC1 bit 6 when using VSC SDP for DCE 11.x

[Leorize]

Friendly ping. Should I resend this patch?

On 5/26/26 7:52 AM, Alex Deucher wrote:
> @Leo (Sunpeng) Li
> , @Wentland, Harry
>
> Can you take a look at this?
>
> On Tue, May 19, 2026 at 3:19 AM Leorize <leorize+oss@xxxxxxxxxxx> wrote:
>> When BT.2020 colorimetry is selected, the driver sends information using
>> VSC SDP but does not set "ignore MSA colorimetry" bit on older GPUs with
>> DCE-based IPs. This causes certain sinks to prefer colorimetry
>> information in DP MSA, resulting in terrible color rendering ("dull"
>> colors) when HDR is enabled.
>>
>> This commit wires up the MISC1 bit 6 for GPUs with DCE 11.x based IPs to
>> correctly configure sinks to ignore colorimetry information in MSA,
>> resolving the color rendering issue.
>>
>> Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/4849
>> Assisted-by: oh-my-pi:GPT-5.5
>> Signed-off-by: Leorize <leorize+oss@xxxxxxxxxxx>
>> ---
>>  .../drm/amd/display/dc/dce/dce_stream_encoder.c   | 15 ++++++++++++++-
>>  .../drm/amd/display/dc/dce/dce_stream_encoder.h   |  3 ++-
>>  2 files changed, 16 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> index ed407e779c12..2c3a20d35fe9 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>> @@ -271,7 +271,6 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
>>         bool use_vsc_sdp_for_colorimetry,
>>         uint32_t enable_sdp_splitting)
>>  {
>> -       (void)use_vsc_sdp_for_colorimetry;
>>         (void)enable_sdp_splitting;
>>         uint32_t h_active_start;
>>         uint32_t v_active_start;
>> @@ -334,6 +333,16 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
>>         if (REG(DP_MSA_MISC))
>>                 misc1 = REG_READ(DP_MSA_MISC);
>>
>> +       /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
>> +        * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
>> +        * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
>> +        * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
>> +        */
>> +       if (use_vsc_sdp_for_colorimetry)
>> +               misc1 = misc1 | 0x40;
>> +       else
>> +               misc1 = misc1 & ~0x40;
>> +
>>         /* set color depth */
>>
>>         switch (hw_crtc_timing.display_color_depth) {
>> @@ -499,6 +508,10 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
>>                                 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
>>                                 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
>>                                 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
>> +       } else {
>> +               /* DCE-only path */
>> +               if (REG(DP_MSA_MISC))
>> +                       REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
>>         }
>>  }
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
>> index 342c0afe6a94..88d6044904d1 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
>> @@ -96,7 +96,8 @@
>>
>>  #define SE_COMMON_REG_LIST(id)\
>>         SE_COMMON_REG_LIST_DCE_BASE(id), \
>> -       SRI(AFMT_CNTL, DIG, id)
>> +       SRI(AFMT_CNTL, DIG, id), \
>> +       SRI(DP_MSA_MISC, DP, id)
>>
>>  #define SE_DCN_REG_LIST(id)\
>>         SE_COMMON_REG_LIST_BASE(id),\
>> --
>> 2.54.0
>>