Re: [PATCH v2 1/8] KVM: arm64: Extract MPIDR computation into a shared header

[Vincent Donnefort]

On Fri, Jun 19, 2026 at 08:07:12AM +0100, Fuad Tabba wrote:
> Extract the vCPU MPIDR computation embedded in reset_mpidr() into a
> kvm_calculate_mpidr() inline in sys_regs.h, so it can be computed
> without duplicating the logic. A follow-up series reuses it to reset
> protected vCPUs at EL2.
> 
> No functional change intended.
> 
> Signed-off-by: Fuad Tabba <tabba@xxxxxxxxxx>

Reviewed-by: Vincent Donnefort <vdonnefort@xxxxxxxxxx>

> ---
>  arch/arm64/kvm/sys_regs.c | 14 +-------------
>  arch/arm64/kvm/sys_regs.h | 19 +++++++++++++++++++
>  2 files changed, 20 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 33c921df19b5..674fabe1d40d 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -976,21 +976,9 @@ static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>  
>  static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
>  {
> -	u64 mpidr;
> +	u64 mpidr = kvm_calculate_mpidr(vcpu);
>  
> -	/*
> -	 * Map the vcpu_id into the first three affinity level fields of
> -	 * the MPIDR. We limit the number of VCPUs in level 0 due to a
> -	 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
> -	 * of the GICv3 to be able to address each CPU directly when
> -	 * sending IPIs.
> -	 */
> -	mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
> -	mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
> -	mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
> -	mpidr |= (1ULL << 31);
>  	vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
> -
>  	return mpidr;
>  }
>  
> diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
> index 2a983664220c..bd56a45abbf9 100644
> --- a/arch/arm64/kvm/sys_regs.h
> +++ b/arch/arm64/kvm/sys_regs.h
> @@ -222,6 +222,25 @@ find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[],
>  	return __inline_bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
>  }
>  
> +static inline u64 kvm_calculate_mpidr(const struct kvm_vcpu *vcpu)
> +{
> +	u64 mpidr;
> +
> +	/*
> +	 * Map the vcpu_id into the first three affinity level fields of
> +	 * the MPIDR. We limit the number of VCPUs in level 0 due to a
> +	 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
> +	 * of the GICv3 to be able to address each CPU directly when
> +	 * sending IPIs.
> +	 */
> +	mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
> +	mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
> +	mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
> +	mpidr |= (1ULL << 31);
> +
> +	return mpidr;
> +}
> +
>  const struct sys_reg_desc *get_reg_by_id(u64 id,
>  					 const struct sys_reg_desc table[],
>  					 unsigned int num);
> -- 
> 2.55.0.rc0.738.g0c8ab3ebcc-goog
>