[PATCH 0/6] clk: renesas: rzg2l: Add RZ/G3L MIPI DSI, LCDC and LVDS clock support

[Biju]

From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Hi all,
 
This series adds clock and reset support for the MIPI DSI, LCDC and LVDS
peripherals on the RZ/G3L (R9A08G046) SoC.
 
The DSI clock path on RZ/G3L is generated by a dedicated fractional PLL
(PLL7), followed by a two-stage divider and a mux that selects between
the LVDS path and the DSI/RGB path, each requiring a different output
duty cycle:
 
 EXTAL->PLL7->[ DIV_DSI_C | DIV_DSI_{A,B}] -> [mux: LVDS | DSI/RGB]-> vclk
 
None of the existing clock types in the driver could express this
hardware, so the series introduces three new clock types plus one small
piece of supporting infrastructure, then wires them up for RZ/G3L:
 
 - Patch 1 adds CLK_TYPE_G3L_DSI_DIV, a two-stage divider
   (power-of-two DIV_DSI_A cascaded with linear DIV_DSI_B) used to
   derive the DSI clock from PLL7.
 
 - Patch 2 adds CLK_TYPE_G3L_PLLDSI for PLL7 itself. PLL7 is a
   fractional PLL with its own parameter search (MR/PR/NIR/NFR) and
   programming sequence, distinct from the existing PLL types in the
   driver.
 
 - Patch 3 is a small preparatory change that splits the divider
   "flag" field used by CLK_TYPE_DIV into separate clock flags and
   divider flags, so that later patches can request divider-specific
   flags (e.g. CLK_DIVIDER_ROUND_CLOSEST) without affecting existing
   CLK_TYPE_DIV users.
 
 - Patch 4 adds CLK_TYPE_G3L_DSI_MUX, a mux that additionally tracks
   and sets the output duty cycle (4/7 for the LVDS path, 1/2 for the
   DSI/RGB path) depending on which parent is selected.
 
 - Patch 5 wires up the above for RZ/G3L: it adds PLL7 and the DSI
   divider/mux chain to the core clock table, and adds module clock
   and reset entries for the MIPI DSI and LCDC peripherals.
 
 - Patch 6 adds the remaining module clock and reset entries for LVDS,
   which shares the same PLL7/mux clock tree set up in patch 5.
 
This series was tested on the RZ/G3L SMARC EVK [add testing details,
e.g. board/display panel used and what was verified - resolution,
clock rates measured, etc.].
 
Patches 1, 2 and 4 depend on each other only loosely (they each add an
independent clock type); patch 3 is a real prerequisite for patch 5,
since patch 5 uses DEF_DIV_FLAGS() on the M2 divider. Patches 1-4 are
core framework changes with no functional effect until patch 5 wires
them into the RZ/G3L clock tables.
 
Looking forward to your review.
 
Best regards,
Biju

Biju Das (6):
  clk: renesas: rzg2l: Add DSI divider clock support for RZ/G3L
  clk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3L
  clk: renesas: rzg2l: Add support for divider flags
  clk: renesas: rzg2l: Add support for RZ/G3L DSI mux
  clk: renesas: r9a08g046-cpg: Add MIPI DSI and LCDC clock/reset entries
  clk: renesas: r9a08g046: Add clock and reset entries for LVDS

 drivers/clk/renesas/r9a08g046-cpg.c |  67 ++++
 drivers/clk/renesas/rzg2l-cpg.c     | 501 +++++++++++++++++++++++++++-
 drivers/clk/renesas/rzg2l-cpg.h     |  31 +-
 3 files changed, 593 insertions(+), 6 deletions(-)

-- 
2.43.0