RE: [PATCH 0/6] clk: renesas: rzg2l: Add RZ/G3L MIPI DSI, LCDC and LVDS clock support

[Biju Das]

Hi,

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 19 June 2026 17:40
> Subject: [PATCH 0/6] clk: renesas: rzg2l: Add RZ/G3L MIPI DSI, LCDC and LVDS clock support
> 
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> Hi all,
> 
> This series adds clock and reset support for the MIPI DSI, LCDC and LVDS peripherals on the RZ/G3L
> (R9A08G046) SoC.
> 
> The DSI clock path on RZ/G3L is generated by a dedicated fractional PLL (PLL7), followed by a two-stage
> divider and a mux that selects between the LVDS path and the DSI/RGB path, each requiring a different
> output duty cycle:
> 
>  EXTAL->PLL7->[ DIV_DSI_C | DIV_DSI_{A,B}] -> [mux: LVDS | DSI/RGB]-> vclk
> 
> None of the existing clock types in the driver could express this hardware, so the series introduces
> three new clock types plus one small piece of supporting infrastructure, then wires them up for RZ/G3L:
> 
>  - Patch 1 adds CLK_TYPE_G3L_DSI_DIV, a two-stage divider
>    (power-of-two DIV_DSI_A cascaded with linear DIV_DSI_B) used to
>    derive the DSI clock from PLL7.
> 
>  - Patch 2 adds CLK_TYPE_G3L_PLLDSI for PLL7 itself. PLL7 is a
>    fractional PLL with its own parameter search (MR/PR/NIR/NFR) and
>    programming sequence, distinct from the existing PLL types in the
>    driver.
> 
>  - Patch 3 is a small preparatory change that splits the divider
>    "flag" field used by CLK_TYPE_DIV into separate clock flags and
>    divider flags, so that later patches can request divider-specific
>    flags (e.g. CLK_DIVIDER_ROUND_CLOSEST) without affecting existing
>    CLK_TYPE_DIV users.
> 
>  - Patch 4 adds CLK_TYPE_G3L_DSI_MUX, a mux that additionally tracks
>    and sets the output duty cycle (4/7 for the LVDS path, 1/2 for the
>    DSI/RGB path) depending on which parent is selected.
> 
>  - Patch 5 wires up the above for RZ/G3L: it adds PLL7 and the DSI
>    divider/mux chain to the core clock table, and adds module clock
>    and reset entries for the MIPI DSI and LCDC peripherals.
> 
>  - Patch 6 adds the remaining module clock and reset entries for LVDS,
>    which shares the same PLL7/mux clock tree set up in patch 5.
> 
> This series was tested on the RZ/G3L SMARC EVK [add testing details, e.g. board/display panel used and
> what was verified - resolution, clock rates measured, etc.].

Tested the below resolution supported by Gechic monitor for DSI/LVDS:

1920x1080-60.00--> DSI (Max resolution tested)
1920x1080-59.94
1280x1024-75.02
1280x1024-60.02
1152x864-75.00
1280x720-60.00--> LVDS (Max resolution tested)
1280x720-59.94
1280x720-50.00
1024x768-75.03
1024x768-70.07
1024x768-60.00
1080x607-59.97
832x624-74.55
800x600-75.00
800x600-72.19
800x600-60.32
800x600-56.25
720x576-50.00
720x480-60.00
720x480-59.94
640x480-75.00
640x480-72.81
640x480-66.67
640x480-60.00
640x480-59.94
720x400-70.08"

Cheers,
Biju