Re: [PATCH v2 0/3] arm64: dts: qcom: kodiak: Enable 4-lane DP via QMP Combo PHY

[Doug Anderson]

Hi,

On Fri, Jun 19, 2026 at 8:34 AM Konrad Dybcio
<konrad.dybcio@xxxxxxxxxxxxxxxx> wrote:
>
> On 5/22/26 5:41 AM, Bjorn Andersson wrote:
> > On Wed, Apr 29, 2026 at 12:10:39PM +0530, Mahadevan P wrote:
> >> This series enables full 4-lane DisplayPort operation on SC7280/kodiak
> >> platforms by wiring up the QMP Combo PHY correctly and consolidating
> >> the DP endpoint configuration in the SoC dtsi.
> >>
> >> Patch 1 adds mode-switch to the QMP Combo PHY node in kodiak.dtsi,
> >> which is required for the PHY to respond to USB-C Alternate Mode
> >> negotiation and switch into 4-lane DP configuration.
> >>
> >> Patch 2 moves the data-lanes property from individual board files into
> >> kodiak.dtsi since the PHY-to-controller wiring is fixed in silicon.
> >> It also removes redundant remote-endpoint and orientation-switch
> >> overrides from qcs6490-rb3gen2 and qcs6490-thundercomm-rubikpi3 that
> >> are already covered by the SoC dtsi.
> >>
> >> Patch 3 updates data-lanes from <0 1> to <0 1 2 3> in kodiak.dtsi now
> >> that mode-switch is in place, enabling the full 4-lane DP link.
> >
> > Are you sure that herobrine has 4 lanes routed on the PCB?
>
> +Doug any chance you still have schematics for that old boy?
>
> Bjorn, perhaps we could switch to a model where we define the max
> capabilities (i.e. 4-lane 8.1 GHz link) in the SoC DTs and only limit
> them as necessary? Not meeting these is borderline a board defect anyway

Bleh, I'd forgotten what a pain it was to look at herobrine schematics
with the whole qcard "abstraction".

My memory and a quick glance at schematics makes me say that herobrine
only has 2 lanes of DP. The problem is that this SoC really wasn't
designed with a laptop in mind. I seem to remember there only being
one USB 3 port and it is muxed with two of the DP lanes (since the SoC
is designed to drive a single Type-C port). In order to support all of
the ports that a laptop should have, you pretty much need to feed that
one USB 3 port into a USB hub and hardcode the DP to always use two
lanes.

The two DP lanes then go to a mux where they can be routed either
towards the left Type C port or the right Type C port.

In terms of whether we can support the 8.1 GHz link speed, I remember
much debate during the project, but I don't recall all the details. I
think the discussion was that we were supposed to support the higher
speeds, but we had to disable them because they weren't working. From
my fuzzy memory, it was unclear whether the problem was known to be
hardware or software related. I can try to dig deeper if it's
relevant.

-Doug