Re: [PATCH v3 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Krzysztof Kozlowski]

On Thu, Jun 18, 2026 at 10:00:32PM +0000, Matthew Leung wrote:
> Add a dedicated schema for the PCIe controllers found on the Hawi
> platform.
> 
> Signed-off-by: Matthew Leung <matthew.leung@xxxxxxxxxxxxxxxx>
> ---
>  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 202 +++++++++++++++++++++
>  1 file changed, 202 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> new file mode 100644
> index 000000000000..fb3145f89f7f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Hawi PCI Express Root Complex
> +
> +maintainers:
> +  - Bjorn Andersson <andersson@xxxxxxxxxx>
> +  - Manivannan Sadhasivam <mani@xxxxxxxxxx>
> +
> +description:
> +  Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
> +  the Synopsys DesignWare PCIe IP.
> +
> +properties:
> +  compatible:
> +    const: qcom,hawi-pcie
> +
> +  reg:
> +    minItems: 5
> +    items:
> +      - description: Qualcomm specific registers
> +      - description: DesignWare PCIe registers
> +      - description: External local bus interface registers
> +      - description: ATU address space
> +      - description: PCIe configuration space
> +      - description: MHI registers

Why is MHI optional?

> +
> +  reg-names:
> +    minItems: 5
> +    items:
> +      - const: parf
> +      - const: dbi
> +      - const: elbi
> +      - const: atu
> +      - const: config
> +      - const: mhi
> +
> +  clocks:
> +    minItems: 6
> +    items:
> +      - description: PCIe Auxiliary clock
> +      - description: PCIe Configuration clock
> +      - description: PCIe Master AXI clock
> +      - description: PCIe Slave AXI clock
> +      - description: PCIe Slave Q2A AXI clock
> +      - description: PCIe Aggre NoC AXI clock
> +      - description: PCIe Config NoC AXI clock

Same here - does that mean that once instance does not have this clock?
If so, mention this in commit msg.

> +
> +  clock-names:
> +    minItems: 6
> +    items:
> +      - const: aux
> +      - const: cfg
> +      - const: bus_master
> +      - const: bus_slave
> +      - const: slave_q2a
> +      - const: noc_aggr
> +      - const: cnoc_sf_axi
> +
> +  interrupts:
> +    minItems: 8
> +    maxItems: 9
> +
> +  interrupt-names:
> +    minItems: 8
> +    items:
> +      - const: msi0
> +      - const: msi1
> +      - const: msi2
> +      - const: msi3
> +      - const: msi4
> +      - const: msi5
> +      - const: msi6
> +      - const: msi7
> +      - const: global

Here as well - why is global optional?

> +
> +  resets:
> +    minItems: 1

Same here?

> +    items:
> +      - description: PCIe core reset
> +      - description: PCIe link down reset
> +
> +  reset-names:
> +    minItems: 1
> +    items:
> +      - const: pci
> +      - const: link_down
> +
> +required:
> +  - power-domains
> +  - resets
> +  - reset-names
> +
> +allOf:
> +  - $ref: qcom,pcie-common.yaml#

Best regards,
Krzysztof