Re: [PATCH 4/5] clk: qcom: gcc-hawi: Add support for global clock controller on Maili

[Konrad Dybcio]

On 6/18/26 7:21 PM, Taniya Das wrote:
> Add support for the global clock controller (GCC) on the Qualcomm Maili
> SoC by extending the Hawi global clock controller since Maili is identical
> to Hawi and has few additional clocks.
> 
> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> ---

[...]

> @@ -3485,6 +3617,11 @@ static struct clk_regmap *gcc_hawi_clocks[] = {
>  	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
>  	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
>  	[GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr,
> +	/*
> +	 * Maili-only clocks: NULL here to size the array to the highest Maili
> +	 * clock index.
> +	 */
> +	[GCC_QUPV3_WRAP_5_S_AHB_CLK] = NULL,

we have:

--- common.c
qcom_cc_really_probe():

...
cc->rclks = rclks; // desc->clks
cc->num_rclks = num_clks; // desc->num_clks
...

 -> devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);

and qcom_cc_clk_hw_get() has:

if (idx >= cc->num_rclks) {
	pr_err("%s: invalid index %u\n", __func__, idx);
	return ERR_PTR(-EINVAL);
}

so I think this should be unnecessary

Besides, is that new set of clocks actually unique to Maili, or
is it bound to a QSPI usecase on the specific QUP?

Konrad