Re: [PATCH 5/13] ASoC: qcom: Add QAIF shared data structures and variant interface

[Harendra Gautam]

On Tue, Jun 23, 2026 at 1:34 PM Harendra Gautam
<harendra.gautam@xxxxxxxxxxxxxxxx> wrote:
>
>
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> On Wed, Jun 17, 2026 at 1:58 AM Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxxxxxxxx> wrote:
>>
>>
>>
>> On 6/5/26 11:37 AM, Harendra Gautam wrote:
>> >
>> > + struct reg_field cif_rddma_shram_wm;
>> > + struct reg_field cif_rddma_active_ch_en;
>> > + struct reg_field cif_rddma_fs_sel;
>> > + struct reg_field cif_rddma_fs_delay;
>> > + struct reg_field cif_rddma_fs_out_gate;
>> > + struct reg_field cif_rddma_intf_dyncclk;
>> > + struct reg_field cif_rddma_en_16bit_unpack;
>> > +
>> Why do we need to use reg_field?, currently this patchset only supports
>> one SoC. reg_field makes sense only when there is change in bit
>> positions across SoCs and if we want to leverage from existing driver.
>>
>> --srini
>>
> Thanks for your comment, change in bit position won't happen for a IP across SoCs. But these bit fields are added with intention to configure bits based on defined value from device tree or based on usecase. Please let me know your thoughts.
> -Harendra

<<resending as last mail was not delivered for a few lists as it was
not plain-text>>
Thanks for your comment, change in bit position won't happen for an IP
across SoCs. But these bit fields are added with the intention to
configure bits based on defined value from device tree or based on
usecase. Please let me know your thoughts.
--Harendra