Re: PROBLEM: Probabilistic segfault on AMD hardware with INVLPGB

[Rik van Riel]

On Tue, 2026-06-23 at 14:28 +0200, Henrik Böving wrote:
> Thanks for the quick response!
> 
> > Upgrading the firmware on the host solved those
> > segfaults for us.
> 
> Our hardware is currently on microcode version 0x0B002162, while the
> advisory you linked names 0x0B00211E as the patched version for our
> model. So I think we should already be sufficiently up to date for
> this
> patch, but I don't know (and couldn't find anything on the web) about
> the details of AMD microcode versioning.

OK, given that you already have the latest firmware,
I suppose it's time to look at your reproducer.

Does your reproducer misbehave only on Turin with
INVLPGB, or also on older AMD CPUs (eg. Bergamo or
Milan) with INVLPGB?

Does the kernel you run have hardening options
enabled, and if so, which ones?

I wonder if one of the hardening things might
be incidentally flushing something when the CPU
gets an IPI, but not when INVLPGB is used.

I believe the actual TLB flushing side of things
should be equivalent for IPI-based vs INVLPGB
flushing, because that code is fairly self
contained, and relatively simple.

I am also not seeing increased segfault rates
on Turin with INVLPGB across a large number of
hosts compared to other large populations of
different CPU types and different kernels.

Lets narrow this thing down.

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