Re: [PATCH v6 07/21] RISC-V: Add Sscfg extension CSR definition

[Atish Patra]

On 6/21/26 11:43 PM, Charlie Jenkins wrote:
> On Mon, Jun 08, 2026 at 11:01:21PM -0700, Atish Patra wrote:
> > From: Kaiwen Xue <kaiwenx@xxxxxxxxxxxx>
> >
> > This adds the scountinhibit CSR definition and S-mode accessible hpmevent
> > bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop
> > counters directly from S-mode without invoking SBI calls to M-mode. It is
> > also used to figure out the counters delegated to S-mode by the M-mode as
> > well.
> >
> > Signed-off-by: Kaiwen Xue <kaiwenx@xxxxxxxxxxxx>
> > Reviewed-by: Clément Léger <cleger@xxxxxxxxxxxx>
> > ---
> >   arch/riscv/include/asm/csr.h | 26 ++++++++++++++++++++++++++
> >   1 file changed, 26 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index b4551a6cf7cb..26cb78dee2fd 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -241,6 +241,31 @@
> >   #define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
> >   #define SMSTATEEN0_SSTATEEN0_SHIFT	63
> >   #define SMSTATEEN0_SSTATEEN0		(_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT)
> > +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */
> > +#ifdef CONFIG_64BIT
> > +#define HPMEVENT_OF			(BIT_ULL(63))
> > +#define HPMEVENT_MINH			(BIT_ULL(62))
> > +#define HPMEVENT_SINH			(BIT_ULL(61))
> > +#define HPMEVENT_UINH			(BIT_ULL(60))
> > +#define HPMEVENT_VSINH			(BIT_ULL(59))
> > +#define HPMEVENT_VUINH			(BIT_ULL(58))
> > +#else
> > +#define HPMEVENTH_OF			(BIT_ULL(31))
> > +#define HPMEVENTH_MINH			(BIT_ULL(30))
> > +#define HPMEVENTH_SINH			(BIT_ULL(29))
> > +#define HPMEVENTH_UINH			(BIT_ULL(28))
> > +#define HPMEVENTH_VSINH			(BIT_ULL(27))
> > +#define HPMEVENTH_VUINH			(BIT_ULL(26))
> Since these are rv32 bits for a 32-bit register, I think these should be
> BIT() instead of BIT_ULL()
>
> > +
> > +#define HPMEVENT_OF			(HPMEVENTH_OF << 32)
> > +#define HPMEVENT_MINH			(HPMEVENTH_MINH << 32)
> > +#define HPMEVENT_SINH			(HPMEVENTH_SINH << 32)
> > +#define HPMEVENT_UINH			(HPMEVENTH_UINH << 32)
> > +#define HPMEVENT_VSINH			(HPMEVENTH_VSINH << 32)
> > +#define HPMEVENT_VUINH			(HPMEVENTH_VUINH << 32)
> These definitions are identical to the rv64 ones, can these be removed
> and can you move the rv64 definitions to be global?

Good catch. Will fix this and the above in v8.

> - Charlie
>
> > +#endif
> > +
> > +#define SISELECT_SSCCFG_BASE		0x40
> >   
> >   /* mseccfg bits */
> >   #define MSECCFG_PMM			ENVCFG_PMM
> > @@ -322,6 +347,7 @@
> >   #define CSR_SCOUNTEREN		0x106
> >   #define CSR_SENVCFG		0x10a
> >   #define CSR_SSTATEEN0		0x10c
> > +#define CSR_SCOUNTINHIBIT	0x120
> >   #define CSR_SSCRATCH		0x140
> >   #define CSR_SEPC		0x141
> >   #define CSR_SCAUSE		0x142
> >
> > --
> > 2.53.0-Meta
> >
> >
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