[PATCH] dmaengine: dw-axi-dmac: Fix cfgr_clk leak in resume error path

[Myeonghun Pak]

axi_dma_resume() enables cfgr_clk before enabling core_clk.  If enabling
core_clk fails, the function currently returns the error without disabling
cfgr_clk.

This path is reachable from dw_probe(), which calls axi_dma_resume()
directly after pm_runtime_get_noresume().  The probe error path only
disables runtime PM, so cfgr_clk can remain prepared and enabled after a
failed probe.

Unwind cfgr_clk when core_clk enable fails so the resume helper keeps the
clock state balanced on all error paths.

Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Co-developed-by: Ijae Kim <ae878000@xxxxxxxxx>
Signed-off-by: Ijae Kim <ae878000@xxxxxxxxx>
Signed-off-by: Myeonghun Pak <mhun512@xxxxxxxxx>

---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 5d74bc29cf..001ab7464e 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1333,12 +1333,17 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
 
 	ret = clk_prepare_enable(chip->core_clk);
 	if (ret < 0)
-		return ret;
+		goto err_disable_cfgr_clk;
 
 	axi_dma_enable(chip);
 	axi_dma_irq_enable(chip);
 
 	return 0;
+
+err_disable_cfgr_clk:
+	clk_disable_unprepare(chip->cfgr_clk);
+
+	return ret;
 }
 
 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev)
-- 
2.47.1