Re: [PATCH v1] drm/bridge: analogix_dp: Apply standard DP training delay helpers

[Vicente Bergas]

On Tue, Jun 23, 2026 at 9:52 AM Damon Ding <damon.ding@xxxxxxxxxxxxxx> wrote:
>
> Replace hardcoded fixed usleep_range() delays during clock recovery and
> channel equalization with drm_dp_link_train_clock_recovery_delay()
> and drm_dp_link_train_channel_eq_delay() helpers.
>
> The original fixed delays are only valid for the case where bit[6:0] of
> DPCD TRAINING_AUX_RD_INTERVAL(0000Eh) is 0x00, while core helpers apply
> spec-compliant timings matching actual receiver capability values.
>
> Additionally, add dpcd buffer to struct analogix_dp_device to cache
> receiver capabilities. Call drm_dp_read_dpcd_caps() at commit entry to
> populate cached DPCD data for subsequent link training steps, and
> prepare for further usage of other DP helper APIs.
>
> Signed-off-by: Damon Ding <damon.ding@xxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ++++++++--
>  drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 1d39a354c3d9..30c0c0b41d5a 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -330,7 +330,7 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
>         u8 voltage_swing, pre_emphasis, training_lane;
>         u8 link_status[DP_LINK_STATUS_SIZE];
>
> -       usleep_range(100, 101);
> +       drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
>
>         lane_count = dp->link_train.lane_count;
>
> @@ -393,7 +393,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
>         u32 reg;
>         u8 link_status[DP_LINK_STATUS_SIZE];
>
> -       usleep_range(400, 401);
> +       drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
>
>         lane_count = dp->link_train.lane_count;
>
> @@ -754,6 +754,12 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
>  {
>         int ret;
>
> +       ret = drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd);
> +       if (ret < 0) {
> +               dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret);
> +               return ret;
> +       }
> +
>         ret = analogix_dp_train_link(dp);
>         if (ret) {
>                 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> index 94348c4e3623..c7997677a286 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -169,6 +169,8 @@ struct analogix_dp_device {
>         bool                    fast_train_enable;
>         bool                    psr_supported;
>
> +       u8 dpcd[DP_RECEIVER_CAP_SIZE];
> +
>         struct analogix_dp_plat_data *plat_data;
>  };
>
> --
> 2.34.1

Tested-by: Vicente Bergas

This patch was tested toghether with
[PATCH v2] drm/bridge: analogix_dp: Fix PE/VS value shift mismatch
during link training

Regards,
  Vicente.