Re: [PATCH v3 1/4] dt-bindings: edac: Add bindings for Xilinx Versal XilSEM

[Krzysztof Kozlowski]

On Thu, Jun 25, 2026 at 02:55:42AM +0530, Rama devi Veggalam wrote:
> Update versal edac device tree bindings for

Everything is update. Pretty useless commit msg.

> Versal Soft Error Mitigation (XilSEM).

A nit, subject: drop second/last, redundant "bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

> 
> Signed-off-by: Rama devi Veggalam <rama.devi.veggalam@xxxxxxx>
> ---
> Changes in v3:
> - Merged XilSEM edac with Versal Edac
> 
> Changes in v2:
> - Changed "xlnx,versal-xilsem-edac" to constant
> - Removed "compatible: in required section
> - Removed "|" in description
> - Removed "items" in compatible
> - Fixed indentation in examples
> - Updated title and description
> ---
>  .../xlnx,versal-ddrmc-edac.yaml               | 22 ++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
> index 12f8e9f350bc..568d2af7de81 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
> @@ -4,17 +4,31 @@
>  $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
> +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) and Soft Error Mitigation (XilSEM)
>  
>  maintainers:
>    - Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxx>
>    - Sai Krishna Potthuri <sai.krishna.potthuri@xxxxxxx>
> +  - Rama Devi Veggalam <rama.devi.veggalam@xxxxxxx>
>  
>  description:
>    The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
>    4X memory interfaces. Versal DDR memory controller has an optional ECC support
>    which correct single bit ECC errors and detect double bit ECC errors.
>  
> +  Xilinx Versal Soft Error Mitigation (XilSEM) is part of the
> +  Platform Loader and Manager (PLM) which runs on the
> +  Platform Management Controller (PMC). XilSEM is responsible for reporting
> +  and optionally correcting soft errors in Configuration Memory of Versal.
> +  The Configuration Memory includes Configuration RAM and
> +  Network on Chip (NoC) peripheral interconnect (NPI) Registers.
> +
> +  The memory is scanned by a hardware controller in the Versal Programmable
> +  Logic (PL). During the scan, if the controller detects any error, be it
> +  correctable or uncorrectable, it reports the error to PLM.
> +  The XilSEM on PLM performs the error validation and notifies the errors to user application.
> +
> +
>  properties:
>    compatible:
>      const: xlnx,versal-ddrmc
> @@ -23,11 +37,13 @@ properties:
>      items:
>        - description: DDR Memory Controller registers
>        - description: NOC registers corresponding to DDR Memory Controller
> +      - description: SEM RTCA Controller registers
>  
>    reg-names:
>      items:
>        - const: base
>        - const: noc
> +      - const: semrtca

You break ABI without any explanation.

NAK, I think I made this point many times already... Please read
writing-bindings doc.

Best regards,
Krzysztof