[PATCH v3 0/2] arm64: dts: socfpga: agilex72: Add initial device tree

[muhammad . nazim . amirul . nazle . asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@xxxxxxxxxx>

This series introduces basic device tree support for the Intel/Altera
Agilex72 SoCFPGA platform, which is a new SoC featuring a heterogeneous
CPU cluster (Cortex-A520 and Cortex-A720 cores).

Patch 1 adds the new compatible strings for Agilex72 to the arm/altera
DT bindings documentation.

Patch 2 introduces the initial DTSI and board-level DTS for the Agilex72
SoCDK. The DTSI covers the core SoC nodes: CPUs, GIC-v3 interrupt
controller with ITS, ARM architectural timer, PSCI, SMMU-v3, OCRAM, and
two UART serial controllers backed by a fixed-clock placeholder. The clock
manager driver for this platform is not yet upstream, so a fixed-clock
at 125 MHz is used as an interim solution for the UART clock, matching
the hardware-confirmed LSP_SP_CLK frequency.

Changes in v3:
- Add UART serial console (uart0, uart1) with fixed-clock placeholder at 125 MHz
- Add aliases and chosen nodes in board DTS for serial console

Changes in v2:
- Applied relevant feedback from Shahsiko's review
- Re-add arm,armv8-timer node which is mandatory for kernel boot
- Rename platform from agilex7-gen2 to agilex72

Nazim Amirul (2):
  dt-bindings: arm: altera: Add Agilex72 SoCFPGA compatible strings
  arm64: dts: socfpga: agilex72: Add initial device tree

 .../devicetree/bindings/arm/altera.yaml       |   6 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../boot/dts/intel/socfpga_agilex72.dtsi      | 156 ++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex72_socdk.dts |  27 +++
 4 files changed, 190 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts

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