Re: [PATCH RFC v4 10/12] reset: zte: Add a zx297520v3 reset driver

[Philipp Zabel]

On Mi, 2026-06-24 at 23:00 +0300, Stefan Dösinger wrote:
> Hi Philipp,
> 
> Am Donnerstag, 18. Juni 2026, 12:24:26 Ostafrikanische Zeit schrieb Philipp 
> Zabel:
> 
> > > +	[ZX297520V3_UART0_RESET]     = { .reg = 0x78,  .mask = BIT(6)  | 
> BIT(7) 
> > > },
> > Is this a single reset line controlled by two bits (do you know what
> > they are)? Or might these actually be two different reset controls that
> > are just always set together?
> 
> I suppose I could expose both bits as separate reset controls in the binding. 
> The lower bit is usually the one that actually resets the device, while the 
> higher one works similarly to PCLK - it disconnects the device from the bus, 
> if asserted. Depending on the device it may or may not leave any residual 
> effect behind after deassert.

So it's not a separate reset.
Whether bus isolation should be controlled together with the reset or
not could be argued, but exposing this as a separate reset control via
the reset API would not be correct.

> The stumbling block is the dwc2 USB driver. It only takes one reset, so I'd 
> have to add another one (or abuse the dwc2-ecc reset) and presumably add a PHY 
> driver for the 3rd reset or add a dwc2-phy reset.

This on the other hand sounds like there is a separate PHY reset line?
If so, I think that should be modeled as a separate control.

regards
Philipp