Re: [PATCH v3 3/5] dmaengine: mcf-edma: Fix interrupt handler for 64 DMA channels

[Frank Li]

On Thu, Jun 25, 2026 at 10:59:39AM +0200, Jean-Michel Hautbois wrote:
> Fix the DMA completion interrupt handler to properly handle all 64
> channels on MCF54418 ColdFire processors.
>
> The previous code used BIT(ch) to test interrupt status bits, which
> causes undefined behavior on 32-bit architectures when ch >= 32 because
> unsigned long is 32 bits and the shift would exceed the type width.
>
> Replace with bitmap_from_u64() and for_each_set_bit() which correctly
> handle 64-bit values on 32-bit systems by using a proper bitmap
> representation.
>
> Fixes: e7a3ff92eaf1 ("dmaengine: fsl-edma: add ColdFire mcf5441x edma support")
> Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@xxxxxxxxxx>
> ---

Reviewed-by: Frank Li <Frank.Li@xxxxxxx>

>  drivers/dma/mcf-edma-main.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
> index f95114829d80..953b20f99f25 100644
> --- a/drivers/dma/mcf-edma-main.c
> +++ b/drivers/dma/mcf-edma-main.c
> @@ -18,7 +18,8 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
>  {
>  	struct fsl_edma_engine *mcf_edma = dev_id;
>  	struct edma_regs *regs = &mcf_edma->regs;
> -	unsigned int ch;
> +	unsigned long ch;
> +	DECLARE_BITMAP(status_mask, 64);
>  	u64 intmap;
>
>  	intmap = ioread32(regs->inth);
> @@ -27,11 +28,11 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
>  	if (!intmap)
>  		return IRQ_NONE;
>
> -	for (ch = 0; ch < mcf_edma->n_chans; ch++) {
> -		if (intmap & BIT(ch)) {
> -			iowrite8(EDMA_MASK_CH(ch), regs->cint);
> -			fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
> -		}
> +	bitmap_from_u64(status_mask, intmap);
> +
> +	for_each_set_bit(ch, status_mask, mcf_edma->n_chans) {
> +		iowrite8(EDMA_MASK_CH(ch), regs->cint);
> +		fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
>  	}
>
>  	return IRQ_HANDLED;
>
> --
> 2.39.5
>