RE: [Intel-wired-lan] [PATCH] ice: propagate ETH56G deskew read errors

[Loktionov, Aleksandr]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@xxxxxxxxxx> On Behalf
> Of Pengpeng Hou
> Sent: Thursday, June 25, 2026 5:03 AM
> To: Nguyen, Anthony L <anthony.l.nguyen@xxxxxxxxx>; Kitszel,
> Przemyslaw <przemyslaw.kitszel@xxxxxxxxx>
> Cc: Andrew Lunn <andrew+netdev@xxxxxxx>; davem@xxxxxxxxxxxxx; Eric
> Dumazet <edumazet@xxxxxxxxxx>; Jakub Kicinski <kuba@xxxxxxxxxx>; Paolo
> Abeni <pabeni@xxxxxxxxxx>; Richard Cochran <richardcochran@xxxxxxxxx>;
> intel-wired-lan@xxxxxxxxxxxxxxxx; netdev@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; pengpeng@xxxxxxxxxxx
> Subject: [Intel-wired-lan] [PATCH] ice: propagate ETH56G deskew read
> errors
> 
> ice_ptp_calc_deskew_eth56g() returns a u32 deskew value, but it also
> returns the negative read_poll_timeout() error when the DESKEW valid
> bit never appears. That converts the negative error into a large
> unsigned deskew contribution, which can then be folded into the RX
> timestamp offset and programmed into hardware.
> 
> Return the deskew value through an output parameter and propagate the
> read error from ice_phy_set_offsets_eth56g() instead of using it as
> offset data.
> 
> Signed-off-by: Pengpeng Hou <pengpeng@xxxxxxxxxxx>

Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@xxxxxxxxx>

I recommend to add Fixes: tag, and proper net or net-next in [PATCH ] to steer properly your fix.

With the best regards
Alex


> ---
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 27 +++++++++++++++-----
> -
>  1 file changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index 8e5f97835954..bd2e31b816a8 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -1736,17 +1736,21 @@ static u32 ice_ptp_calc_bitslip_eth56g(struct
> ice_hw *hw, u8 port, u32 bs,
>   * @ds: deskew multiplier
>   * @rs: RS-FEC enabled
>   * @spd: link speed
> + * @deskew: calculated deskew value
>   *
> - * Return: calculated deskew value
> + * Return: 0 on success, negative error code otherwise
>   */
> -static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32
> ds,
> -				      bool rs, enum ice_eth56g_link_spd
> spd)
> +static int ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32
> ds,
> +				      bool rs, enum ice_eth56g_link_spd
> spd,
> +				      u32 *deskew)
>  {
>  	u32 deskew_i, deskew_f;
>  	int err;
> 
> -	if (!ds)
> +	if (!ds) {
> +		*deskew = 0;
>  		return 0;
> +	}
> 
>  	read_poll_timeout(ice_read_ptp_reg_eth56g, err,
>  			  FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i),
> 500, @@ -1766,7 +1770,9 @@ static u32
> ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds,
>  	deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT,
> deskew_i);
>  	/* Shift 3 fractional bits to the end of the integer part */
>  	deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W -
> PHY_REG_DESKEW_0_RLEVEL_FRAC_W;
> -	return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
> +	*deskew = mul_u32_u32_fx_q9(deskew_i | deskew_f, ds);
> +
> +	return 0;
>  }
> 
>  /**
> @@ -1789,6 +1795,7 @@ static int ice_phy_set_offsets_eth56g(struct
> ice_hw *hw, u8 port,  {
>  	u32 rx_offset, tx_offset, bs_ds;
>  	bool onestep, sfd;
> +	int err;
> 
>  	onestep = hw->ptp.phy.eth56g.onestep_ena;
>  	sfd = hw->ptp.phy.eth56g.sfd_ena;
> @@ -1805,11 +1812,15 @@ static int ice_phy_set_offsets_eth56g(struct
> ice_hw *hw, u8 port,
>  	if (sfd)
>  		rx_offset = add_u32_u32_fx(rx_offset, cfg-
> >rx_offset.sfd);
> 
> -	if (spd < ICE_ETH56G_LNK_SPD_40G)
> +	if (spd < ICE_ETH56G_LNK_SPD_40G) {
>  		bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc,
> rs,
>  						    spd);
> -	else
> -		bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs,
> spd);
> +	} else {
> +		err = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs,
> spd,
> +						 &bs_ds);
> +		if (err)
> +			return err;
> +	}
>  	rx_offset = add_u32_u32_fx(rx_offset, bs_ds);
>  	rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT |
>  		     ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC;
> --
> 2.50.1 (Apple Git-155)