Re: [PATCH v5 0/7] drm/verisilicon: add Nuvoton MA35D1 DCU Lite support

[Icenowy Zheng]

在 2026-06-25四的 17:44 +0800，Joey Lu写道：
> This series adds support for the Verisilicon DCUltraLite display
> controller as integrated in the Nuvoton MA35D1 SoC.
> 
> The Verisilicon DC driver and its DT binding were originally written
> by
> Icenowy Zheng <zhengxingda@xxxxxxxxxxx> for the T-Head TH1520 SoC,
> which
> carries a DC8200 IP block.  The present series builds on that
> foundation
> with gratitude to Icenowy for the original work.
> 
> The DCUltraLite is a different variant in the DC IP family.  While
> the two
> IPs share a broadly similar register layout, a number of differences
> prevent the existing driver from working on the MA35D1 without
> modification:
> 
>   - No CONFIG_EX commit path: the DC8200 staging registers
>     (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG,
>     PANEL_CONFIG_EX) are absent.  The DCUltraLite uses enable (bit 0)
> and
>     reset (bit 4) bits in FB_CONFIG for direct framebuffer updates,
> and
>     requires a per-frame VALID bit toggle (FB_CONFIG bit 3) to latch
>     configuration changes.
> 
>   - No PANEL_START register: panel output begins when
>     PANEL_CONFIG.RUNNING is set; the DC8200 multi-display sync start
>     register at 0x1CCC does not exist.
> 
>   - Different IRQ registers: DISP_IRQ_STA at 0x147C / DISP_IRQ_EN at
>     0x1480, versus the DC8200's TOP_IRQ_ACK at 0x0010 / TOP_IRQ_EN at
>     0x0014.
> 
>   - Simpler clock topology: two clocks ("core" bus gate and "pix0"
> pixel
>     divider); no axi or ahb clocks required.
> 
>   - Single display output: no per-output indexing beyond index 0 is
>     needed.
> 
>   - Hardware-discoverable identity: the DCUltraLite exposes chip
> identity
>     registers whose model field reads 0x0 (revision 0x5560,
>     customer_id 0x305), allowing the existing vs_fill_chip_identity()
>     path to identify the variant purely through register reads.
> 
> Patch 1 generalises the verisilicon,dc DT binding to accommodate the
> Nuvoton MA35D1 SoC-specific compatible and the variant's two-clock,
> one-reset, single-port topology.
> 
> Patch 2 adds the register-level macros needed by the DC8000 ops.
> 
> Patches 3-5 introduce the driver changes in three logical steps: the
> vs_dc_funcs hardware ops vtable with DC8200 ops extracted into
> vs_dc8200.c; making axi/ahb clocks optional as a separate atomic
> change;
> and the DC8000 ops in vs_dc8000.c.  Patch 6 adds the DCUltraLite HWDB
> entry that gates hardware recognition once all support is in place.
> 
> Patch 7 adds the Kconfig dependency on ARCH_MA35, placed last because
> it
> is only meaningful after the HWDB entry is added.
> 
> All patches have been tested on Nuvoton MA35D1 hardware.

I also tested these patches on TH1520, and it seems to show no
regression.

Thanks,
Icenowy

> 
> Changes from v4:
>   - [dt-bindings] Kept clock and reset item descriptions in the
> global
>     clocks:/resets: properties; per-compatible sections only
> constrain
>     minItems/maxItems and override clock-names items for
> nuvoton,ma35d1-dcu.
>   - [dt-bindings] Dropped redundant global minItems/maxItems on
> clocks:
>     and clock-names:.
>   - [dt-bindings] Dropped the extra-space typo fix in port@0
> description
>     to keep the patch atomic; left for a separate patch later.
>   - [ops] Renamed crtc_enable/crtc_disable hooks to crtc_enable_ex/
>     crtc_disable_ex.
>   - [ops] Added unified IRQ bit definitions; each irq_ack()
> implementation
>     now translates hardware-specific bits before returning.
>   - [clocks] Split the axi/ahb optional-clock change into its own
> patch
>     for atomicity.
>   - [hwdb] Simplified the commit message for patch 6.
>   - [kconfig] Simplified the commit message for patch 7.
> 
> Joey Lu (7):
>   dt-bindings: display: verisilicon,dc: generalize for single-output
>     variants
>   drm/verisilicon: add register-level macros for DC8000
>   drm/verisilicon: introduce per-variant hardware ops table
>   drm/verisilicon: make axi and ahb clocks optional
>   drm/verisilicon: add DC8000 (DCUltraLite) display controller
> support
>   drm/verisilicon: add DCUltraLite chip identity to HWDB
>   drm/verisilicon: extend Kconfig to support ARCH_MA35 platforms
> 
>  .../bindings/display/verisilicon,dc.yaml      |  57 +++++++++
>  drivers/gpu/drm/verisilicon/Kconfig           |   2 +-
>  drivers/gpu/drm/verisilicon/Makefile          |   2 +-
>  drivers/gpu/drm/verisilicon/vs_bridge.c       |  20 +--
>  drivers/gpu/drm/verisilicon/vs_crtc.c         |  38 +++++-
>  drivers/gpu/drm/verisilicon/vs_crtc_regs.h    |   1 +
>  drivers/gpu/drm/verisilicon/vs_dc.c           |  13 +-
>  drivers/gpu/drm/verisilicon/vs_dc.h           |  33 +++++
>  drivers/gpu/drm/verisilicon/vs_dc8000.c       |  86 +++++++++++++
>  drivers/gpu/drm/verisilicon/vs_dc8200.c       | 115
> ++++++++++++++++++
>  drivers/gpu/drm/verisilicon/vs_drm.c          |   5 +-
>  drivers/gpu/drm/verisilicon/vs_drm.h          |   8 ++
>  drivers/gpu/drm/verisilicon/vs_hwdb.c         |  14 +++
>  drivers/gpu/drm/verisilicon/vs_hwdb.h         |   6 +
>  .../gpu/drm/verisilicon/vs_primary_plane.c    |  32 +----
>  .../drm/verisilicon/vs_primary_plane_regs.h   |   3 +
>  16 files changed, 378 insertions(+), 57 deletions(-)
>  create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8000.c
>  create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8200.c