Re: [PATCH v3 00/15] drm/tidss: Add BeagleY-AI display support (and some more)

[Shubham]

Hi Tomi,

A big update on the Raspberry Pi Touch Display 2 (5-inch, native ILI9881C
MIPI-DSI, 720x1280, 2 lanes) bring-up on BeagleY-AI (AM67A/J722S), still on
Robert's v7.0.x-arm64-k3 tree (7.0.11-arm64-k3-r20): tidss + cdns-dsi +
cdns-dphy, DSS = ti,am62p-dss (dispc_am625_feats).

The earlier "tidss comes up before the DSI bridge is added" problem is
resolved (cdns-dsi now adds its input bridge in probe, so tidss attaches it),
and after fixing two more issues the panel is now alive -- but I'm stuck on
one last step and would value your read.

What is now confirmed working
-----------------------------

  - DSI-1 connector is created, tidss initializes, no probe errors, nothing
    left in /sys/kernel/debug/devices_deferred.
  - The panel is ALIVE and initialized: a DCS read of GET_POWER_MODE (0x0A)
    returns 0x9c (booster on, sleep-out, display-on). So the LP command path
    over the cdns works and the ILI9881C processed its init sequence.
  - cdns-dsi looks healthy while a test pattern streams:
      MCTL_MAIN_STS = 0x0000000F  (PLL_LOCKED + CLK_LANE_RDY + DATA_LANE_RDY 0/1)
      MCTL_DPHY_ERR = 0x00000000  (no D-PHY errors)
      VID_MODE_STS  = 0x00000001  (VSG_RUNNING, no error bits)
      MCTL_LANE_STS -> clock lane in HS
      VID_MAIN_CTL  = 0x80A0FE00  (RGB888, packed-pixel DT 0x3E)
      VID_HSIZE2 hact = 2160 (720*3), VID_VSIZE2 vact = 1280
    cdns-dphy PLL locks (no "Failed to lock PLL").
  - The DSS is scanning out:
      modetest -M tidss -s <dsi>@<crtc>:720x1280 -v  ->  steady 60.01 Hz.

(For reference, the two fixes that got the panel this far were: nesting the
DSS port@1 under the controller's "ports" node in my overlay, and correcting
the BeagleY-AI MIPI mux OE polarity -- it is active-low, and the data-lane
mux had been left disabled while i2c still worked through a separate path.)

The problem: cdns data lanes never transmit
-------------------------------------------

Sampling MCTL_LANE_STS 20000 times while the pattern is actively streaming
(modetest -v at 60 Hz, from a second session):

  DATA0 states: {'IDLE': 20000}
  DATA1 states: {'IDLE': 20000}

So the clock lane is in HS and the VSG reports "running", but the data lanes
are 100% IDLE -- the cdns is in video mode yet never emits pixel packets.
The DSS VP does not appear to feed the cdns DPI input even though the VP
timing generator runs at 60 Hz, and the panel (correctly initialized) just
shows backlight, no image.

What I have ruled out
---------------------

  - Videoport selection: I tried the DSI on DSS port@1 (VP2 = DISPC_VP_DPI)
    and on DSS port@0 (VP1 = DISPC_VP_INTERNAL). Identical result, data lanes
    IDLE in both.
  - tidss correctly treats the cdns as internal: the bridge of_node
    compatible "ti,j721e-dsi" is in tidss_internal_bridge_compatibles[], so
    dpi_output is false and it does not touch ti,am625-dss-dpi0-clk-ctrl for
    this videoport.
  - Overlay/graph: cdns DSI_OUTPUT_PORT=0 (panel) / DSI_INPUT_PORT=1 (DSS)
    wired accordingly; panel attaches; no -ENODEV; VID timing is correct.

Questions
---------

  1. On AM67A/J722S, what internally connects a DSS video port's DPI to the
     cdns-dsi DPI input, and is there a clock/enable/routing step (beyond the
     DT graph and dpi0-clk-ctrl, which tidss skips for the internal path)
     required for the DSS to actually feed the cdns?
  2. Which DSS VP is wired to the internal DSI on this SoC (VP1/INTERNAL vs
     VP2/DPI), and does the DISPC_VP_INTERNAL path need any handling that the
     DISPC_VP_DPI path does not get?
  3. Any reason the cdns VSG would report VSG_RUNNING with the clock lane in
     HS and both data lanes "ready", yet never drive the data lanes (no pixel
     packets) while the DSS VP is visibly scanning at 60 Hz?

I'm happy to share the full overlay, dmesg and register dumps, and to test
patches.

Thanks,
Shubham