Re: [RFC PATCH 2/3] dt-bindings: riscv: Add Worlds per-hart properties

[Yu-Chien Peter Lin]

Hi Conor,

On Mon, Jun 22, 2026 at 06:12:47PM +0100, Conor Dooley wrote:
> On Fri, Jun 19, 2026 at 06:58:33PM +0800, Yu-Chien Peter Lin wrote:
> > Add per-hart DT properties for RISC-V Worlds architecture:
> > riscv,pmwid, riscv,pmwidlist, and riscv,pmlwidlist. These
> > platform-defined values are primarily used by M-mode firmware
> > to configure World ID CSRs and restrict WID usage across
> > privilege levels.
> > 
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@xxxxxxxxxx>
> > ---
> >  .../devicetree/bindings/riscv/cpus.yaml       | 21 +++++
> >  .../devicetree/bindings/riscv/worlds.yaml     | 77 +++++++++++++++++++
> >  2 files changed, 98 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/riscv/worlds.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 5feeb2203050..4b5778b6d3e7 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -26,6 +26,7 @@ description: |
> >  allOf:
> >    - $ref: /schemas/cpu.yaml#
> >    - $ref: extensions.yaml
> > +  - $ref: worlds.yaml
> >    - if:
> >        not:
> >          properties:
> > @@ -120,11 +121,31 @@ properties:
> >        thead systems where the vector register length is not identical on all harts, or
> >        the vlenb CSR is not available.
> >  
> > +  riscv,pmwid:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Platform-defined M-mode World ID (WID) assigned to this hart.
> > +    minimum: 0
> > +    maximum: 63
> > +
> > +  riscv,pmwidlist:
> > +    $ref: /schemas/types.yaml#/definitions/uint64
> > +    description:
> > +      Platform-defined bitmap of M-mode World IDs (WIDs) that this hart may use.
> 
> I don't understand what the difference is between this property and the
> one before it are.
> Is this one meant to be used by m-mode software to then select one which
> will appear in riscv,pmwid?

pmwid (single value) is the reset default, while pmwidlist (bitmap)
defines the allowed set. The root-of-trust M-mode software may select
an allowed value from the pmwidlist and write it to the mwid CSR.

> 
> > +
> > +  riscv,pmlwidlist:
> > +    $ref: /schemas/types.yaml#/definitions/uint64
> > +    description:
> > +      Platform-defined bitmap of World IDs (WIDs) that S-mode and U-mode may use
> > +      on this hart.
> > +
> >    # RISC-V has multiple properties for cache op block sizes as the sizes
> >    # differ between individual CBO extensions
> >    cache-op-block-size: false
> >    # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
> >    timebase-frequency: false
> 
> > +  # RISC-V requires 'riscv,nworlds' in /cpus, so disallow it here
> > +  riscv,nworlds: false
> 
> Isn't this pointless? Nothing ever defines riscv,nworlds as a cpu level
> property so there's no need to disallow it?

Okay, thanks for the catch, will drop this.

Best regards,
Peter Lin

> 
> >  
> >    interrupt-controller:
> >      type: object
> > diff --git a/Documentation/devicetree/bindings/riscv/worlds.yaml b/Documentation/devicetree/bindings/riscv/worlds.yaml
> > new file mode 100644
> > index 000000000000..cc8b3747591e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/worlds.yaml
> > @@ -0,0 +1,77 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/worlds.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: RISC-V Worlds Extension
> > +
> > +maintainers:
> > +  - Yu-Chien Peter Lin <peter.lin@xxxxxxxxxx>
> > +
> > +description: |
> > +  The RISC-V Worlds ISA extension, as described in the RISC-V Privileged
> > +  Specification, adds World ID tagging for context isolation.
> > +
> > +  This binding describes the system-wide Worlds configuration for the /cpus node
> > +  and is used alongside per-hart Worlds-related properties such as riscv,pmwid in
> > +  the RISC-V CPU binding and Worlds-related ISA extensions enumerated via
> > +  riscv,isa-extensions.
> > +
> > +select:
> > +  properties:
> > +    $nodename:
> > +      pattern: "^cpus$"
> > +
> > +properties:
> > +  riscv,nworlds:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description: |
> > +      Number of World IDs (WIDs) supported by the platform. This is a system-wide
> > +      property that describes the total number of isolation contexts available.
> > +      Hardware components such as the WorldGuard Checker use this to determine
> > +      the valid range of WID values.
> > +    minimum: 2
> > +    maximum: 64
> > +
> > +additionalProperties: true
> > +
> > +examples:
> > +  - |
> > +    // Example: System with 4 World IDs
> > +    cpus {
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +        timebase-frequency = <1000000>;
> > +        riscv,nworlds = <4>;
> > +
> > +        cpu@0 {
> > +            device_type = "cpu";
> > +            reg = <0>;
> > +            compatible = "sifive,bullet0", "riscv";
> > +            riscv,isa-base = "rv64i";
> > +            riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
> > +            riscv,pmwid = <0>;
> > +
> > +            interrupt-controller {
> > +                #interrupt-cells = <1>;
> > +                compatible = "riscv,cpu-intc";
> > +                interrupt-controller;
> > +            };
> > +        };
> > +
> > +        cpu@1 {
> > +            device_type = "cpu";
> > +            reg = <1>;
> > +            compatible = "sifive,bullet0", "riscv";
> > +            riscv,isa-base = "rv64i";
> > +            riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
> > +            riscv,pmwid = <1>;
> > +
> > +            interrupt-controller {
> > +                #interrupt-cells = <1>;
> > +                compatible = "riscv,cpu-intc";
> > +                interrupt-controller;
> > +            };
> > +        };
> > +    };
> > -- 
> > 2.43.7
> >