Re: [PATCH v8 12/14] x86/mm: Move flush_tlb_info back to the stack

[Thomas Gleixner]

On Tue, Jun 16 2026 at 19:11, Chuyi Zhou wrote:

> flush_tlb_info benefits from cacheline alignment, but using
> cacheline-aligned stack storage directly can grow stack usage too much on
> configurations with large SMP_CACHE_BYTES values[1]. That problem caused

What's the link for when you can explain it in prose? Right after that
you tell that this caused 515... to be reverted.

> commit 515ab7c41306 ("x86/mm: Align TLB invalidation info") to be
> reverted. Commit 3db6d5a5ecaf ("x86/mm/tlb: Remove 'struct flush_tlb_info'
> from the stack") moved flush_tlb_info to per-CPU storage, which avoided the
>
>                    base   on-stack-aligned  on-stack-not-aligned
>                    ----       ---------      -----------
> avg (usec/op)     2.5278       2.5261         2.5508
> stddev            0.0007       0.0027         0.0023
>
> The benchmark results show that the average latency difference between
> the baseline (base) and the properly aligned stack variable
> (on-stack-aligned) is within the standard deviation (stddev). This
> indicates that the variations are caused by testing noise, and reverting
> to a stack variable with proper alignment causes no performance
> regression compared to the per-CPU implementation. The unaligned version
> (on-stack-not-aligned) shows a minor performance drop. This demonstrates
> that we can shorten the CPU-pinned/preemption-disabled section without

the ... disabled section can be shortened...